Patents by Inventor Rishabh Sehgal

Rishabh Sehgal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuits, devices, and methods for reducing flip-flop short-circuit currents
    Patent number: 12289108
    Abstract: A circuit may include (1) an external input, (2) an external output, (3) a flip-flop subcircuit including (A) a first sequential subcircuit for reading data-input signals from the external input, the first sequential subcircuit including a first internal input coupled to the external input and a first internal output and (B) a second sequential subcircuit for outputting data-output signals to the external output, the second sequential subcircuit including a second internal input coupled to the first internal output of the first sequential subcircuit and a second internal output coupled to the external output, and (4) a hysteresis subcircuit coupled to the external output and configured to reduce a short-circuit current of the circuit. Various other devices, systems, and methods are also disclosed.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: April 29, 2025
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Saurabh Kumar, Rishabh Sehgal
  • CIRCUITS, DEVICES, AND METHODS FOR REDUCING FLIP-FLOP SHORT-CIRCUIT CURRENTS
    Publication number: 20240372540
    Abstract: A circuit may include (1) an external input, (2) an external output, (3) a flip-flop subcircuit including (A) a first sequential subcircuit for reading data-input signals from the external input, the first sequential subcircuit including a first internal input coupled to the external input and a first internal output and (B) a second sequential subcircuit for outputting data-output signals to the external output, the second sequential subcircuit including a second internal input coupled to the first internal output of the first sequential subcircuit and a second internal output coupled to the external output, and (4) a hysteresis subcircuit coupled to the external output and configured to reduce a short-circuit current of the circuit. Various other devices, systems, and methods are also disclosed.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 7, 2024
    Inventors: Saurabh Kumar, Rishabh Sehgal