Abstract: Systems and methods are disclosed for a decision tree processing system. A machine learning decision tree architecture, such as a Random Forest, can be very intense in computation and can require a large amount of memory. To account for such, the systems and methods herein can implement a hardware approach where the training for the decision trees can be performed in advance via firmware (or an algorithm implemented via any other software and processing system) and the hardware can implement a circuit to process the decision trees. In some examples, multiple decision trees may be processed in parallel. Also, a circuit can compute the best outcome for a decision tree based on a random feature and a pre-determined threshold for the random feature assigned to each node of the decision tree.

Abstract: A plurality of configuration sets are used with a detector coupled to a decoder. A processor is coupled to the memory registers and the detector and operable to load a first one of the configuration sets into the detector. The detector to attempts detection of the bits in the digital stream for a first iteration between the detector and the decoder using the first configuration set. After the first iteration, a second one of the configuration sets is loaded into the detector. The second configuration set is different than the first configuration set. The detector to attempts detection of the bits in the digital stream for a second iteration between the detector and the decoder using the second configuration set.

Abstract: In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.

Abstract: In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.

Abstract: An apparatus can include a circuit configured to process an input signal using a set of channel parameters. The circuit can produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit can further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit can perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.

Abstract: In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.

Abstract: In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.

Abstract: An apparatus may include a circuit configured to process an input signal using a set of channel parameters. The circuit may produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit may further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit may perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.

Abstract: A system may comprise a finite impulse response circuit configured to receive one or more samples of a first signal and generate an equalized signal based on the plurality of samples of the input signal and one or more updatable tap coefficients. The system may include an adaptation circuit configured to update the one or more updatable tap coefficients based on the plurality of samples of the input signal. The system may further comprise a recovery circuit configured to accumulate one or more retuning values based on the plurality of samples of the input signal and, in response to an error condition, generate one or more retuned tap coefficients for the finite impulse response circuit based on the one or more retuning values and replace the one or more updatable parameters with the one or more retuned parameters.

Abstract: In certain embodiments, an apparatus may comprise a circuit configured to receive a plurality of samples of an input signal. The circuit may update one or more equalizer parameters using partial zero forcing equalization. Further, the circuit may generate an equalized signal based on the plurality of samples of the input signal and the one or more equalizer parameters.

Abstract: A circuit may be configured to adaptively combine two or more waveforms into a single waveform. The circuit can generate weighting factors based on received error signals, and can apply the weighting factors to the two or waveforms to be combined. In some examples, a circuit can be configured to receive input signals, receive error signals, generating a weighting coefficient based on at least some of the error signals, and determine an output signal based on the weighting coefficient and the input signals.

Abstract: Multiple input single output (MISO) systems and processes are presented that can adaptively equalize multiple signals to produce an output. In some examples, the MISO systems can include a fast transversal recursive least square (RLS) algorithm to produce the output. Fast transversal RLS algorithms can be less complex than other RLS algorithms. In some examples, the fast transversal RLS algorithm may be optimized to have no division operations. The MISO system may have two or more inputs.

Abstract: A circuit may be configured to adaptively combine two or more waveforms into a single waveform. The circuit can generate weighting factors based on received error signals, and can apply the weighting factors to the two or waveforms to be combined.

Abstract: Apparatus and method for recovering data from a multi-channel input signal, such as but not limited to a readback signal from a bit patterned medium (BPM) having a plurality of subtracks. In accordance with some embodiments, a single input single output (SISO) equalizer is adapted to generate equalized outputs responsive to alternating subchannels of the multi-channel input signal. A detector is adapted to generate estimates of data symbols represented by the input signal responsive to the equalized outputs. A switching circuit is adapted to switch in different equalizer coefficients for use by the SISO equalizer for each of the alternating subchannels in the input signal.

Abstract: Apparatus and method for recovering data from a multi-channel input signal, such as but not limited to a readback signal from a bit patterned medium (BPM) having a plurality of subtracks. In accordance with some embodiments, a single input single output (SISO) equalizer is adapted to generate equalized outputs responsive to alternating subchannels of the multi-channel input signal. A detector is adapted to generate estimates of data symbols represented by the input signal responsive to the equalized outputs. A switching circuit is adapted to switch in different equalizer coefficients for use by the SISO equalizer for each of the alternating subchannels in the input signal.

Abstract: A signal detector/decoder is implemented in multiple stages. The beginning stage is configured to input channel data bits and to output hard data bits based on the channel bits and a maximum likelihood (ML) path. The next stage includes a postcoder coupled to receive channel domain information from the first stage and to convert the channel domain information to user domain information. The final stage includes a reliability unit coupled to receive the user domain information from the postcoder and to output user domain soft information for the hard data bits based on the ML path estimation and the user domain information.

Abstract: A signal detector/decoder is implemented in multiple stages. The beginning stage is configured to input channel data bits and to output hard data bits based on the channel bits and a maximum likelihood (ML) path. The next stage includes a postcoder coupled to receive channel domain information from the first stage and to convert the channel domain information to user domain information. The final stage includes a reliability unit coupled to receive the user domain information from the postcoder and to output user domain soft information for the hard data bits based on the ML path estimation and the user domain information.