Abstract: Apparatuses, systems, and techniques to perform operations in a processor asynchronously. In at least one embodiment, a processor performs perform at least one tensor instruction concurrently with one or more other instructions based, at least in part, on one or more indicators of the tensor instruction being asynchronous.

Abstract: Apparatuses, systems, and techniques to perform an instruction to use storage to store information to be used exclusively by one or more tensor operations. In at least one embodiment, a processor retrieves information from storage that exclusively stores matrix information in response to an instruction and performs a multiplication computation using said matrix information.

Abstract: Apparatuses, systems, and techniques to perform an matrix multiply accumulate (MMA) instruction to cause a plurality of portions of an MMA operation to be performed using a corresponding plurality of MMA accelerators. In at least one embodiment, a processor retrieves a plurality of matrix information from a memory that exclusively stores and performs a multiplication computation using said matrix information.

Abstract: Apparatuses, systems, and techniques to adapt instructions in a SIMT architecture for execution on serial execution units. In at least one embodiment, a predicate mask is initialized to identify a group of active threads associated with an instruction. The predicate mask is initialized with an inherited predicate of the instruction. The instruction is executed for a set of one or more threads selected from the group of active threads using a serial execution unit.

Abstract: Apparatuses, systems, and techniques to cause to cause one or more first storage address sizes to be converted into one or more second storage address sizes. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more first storage address sizes to be converted to one or more second storage address sizes based, at least in part, on one or more identifiers of one or more physical storage locations corresponding to either of the one or more first storage address sizes or the one or more second storage address sizes.

Abstract: Apparatuses, systems, and techniques to compile and modify software programs. In at least one embodiment, a software program is to be modified to initialize information to be used by one or more application programming interfaces (APIs).

Abstract: Apparatuses, systems, and techniques to compile and modify software programs. In at least one embodiment, a software program is to be modified to initialize information to be used by one or more application programming interfaces (APIs).

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

Abstract: Apparatuses, systems, and techniques to adapt instructions in a SIMT architecture for execution on serial execution units. In at least one embodiment, a set of one or more threads is selected from a group of active threads associated with an instruction and the instruction is executed for the set of one or more threads on a serial execution unit.

Abstract: Various embodiments include a parallel processing computer system that enables parallel instances of a program to synchronize at disparate addresses in memory. When the parallel program instances need to exchange data, the program instances synchronize based on a mask that identifies the program instances that are synchronizing. As each program instance reaches the point of synchronization, the program instance blocks and waits for all other program instances to reach the point of synchronization. When all program instances have reached the point of synchronization, at least one program instance executes a synchronous operation to exchange data. The program instances then continue execution at respective and disparate return addresses.

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until matrix multiply-accumulate (MMA) memory transactions are performed.

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to indicate whether matrix multiply-accumulate (MMA) memory operations are complete.

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause two or more other computational operations to be performed by two or more streaming multiprocessors (SMs).

Abstract: Apparatuses, systems, and techniques to adapt instructions in a SIMT architecture for execution on serial execution units. In at least one embodiment, a set of one or more threads is selected from a group of active threads associated with an instruction and the instruction is executed for the set of one or more threads on a serial execution unit.

Abstract: Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.

Abstract: Apparatuses, systems, and techniques to cause data to be selectively stored in one or more memory locations. In at least one embodiment, a processor is to cause data to be selectively stored in one or more memory locations based, at least in part, on one or more threads to use the data.

Abstract: Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.