Abstract: A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

Abstract: A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

Abstract: In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.

Abstract: In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.

Abstract: On a silicon substrate in which boron (B) has been introduced, an n.sup.+ polysilicon film and a tungsten silicide film are sequentially deposited, with a gate oxide film being interposed between the substrate and the polysilicon film, to form a gate electrode. A sidewall of p.sup.+ polysilicon is formed at each side of said gate electrode. A source/drain diffusion layer of an n.sup.+ region is self-aligned with a side edge portion of the gate electrode including the sidewall. The formation of the sidewall is performed after the source/drain diffusion layers have been formed using a dummy sidewall. The gate structure thus formed has a steep potential gradient in the lateral direction of channel region. In the field effect transistor thus formed, the short channel effect is efficiently suppressed.

Abstract: In a field intensity relaxation of the drain end of a MOSFET, a projective area is not increased with a reduced electrostatic coupling of the source or drain with the gate. The MOSFET satisfying such condition is fabricated on the SOIS film formed by processes of the lateral vapor phase epitaxial growth and the like. A U-shape low concentration impurity region is provided on a gate electrode through a gate dioxide film and high concentration impurity regions are formed at the tops of protrusions. The gate electrode is embedded in insulation films, and the transistor region is fabricated by the lateral vapor phase epitaxial growth and the like.

Abstract: On the substrate of an integrated circuit chip is deposited a first insulating layer in which a low resistivity semiconductor region is subsequently formed. An insulating film is formed on a side wall of the low resistivity semiconductor region. A slit is formed in the first insulating layer so that a portion of the substrate and a portion of the insulating film are exposed. First, second and third semiconductor layers of different conductivity types are epitaxially grown in the slit so that the second layer is in contact with the exposed insulating film. A second insulating layer is deposited on the chip. Through the second insulating layer first, second and third electrodes are brought into contact with the first and third semiconductor layers and with the low resistivity semiconductor region. Due to the stacking of epitaxial layers of different conductivity types, the impurity profiles of the epitaxial layers can be precisely controlled.

Abstract: In a field intensity relaxation of the drain end of a MOSFET, a projective area is not increased with a reduced electrostatic coupling of the source or drain with the gate. The MOSFET satisfying such condition is fabricated on the SOIS film formed by processes of the lateral vapor phase epitaxial growth and the like. A U-shape low concentration impurity region is provided on a gate electrode through a gate dioxide film and high concentration impurity regions are formed at the tops of protrusions. The gate electrode is embedded in insulation films, and the transistor region is fabricated by the lateral vapor phase epitaxial growth and the like.