Abstract: An imaging device comprises a semiconductor substrate including an array of pixel cells. Each pixel cell comprising an individually addressable pixel circuit for accumulating charge resulting from radiation incident on a pixel detector. The pixel circuit and the pixel detector can either be implemented on a single substrate, or on two substrates bonded together. The charge storage device can be a transistor, for example one of a pair of FET transistors connected as a cascade amplification stage. An imaging plane can be made up of one imaging device or a plurality of imaging devices tiled to form a mosaic. The imaging devices may be configured as a slot for certain applications, the slit or slot being scanned over the imaging plane. Control electronics can include addressing logic for addressing individual pixel circuits for reading accumulated charge from the pixel circuits.

Abstract: A semiconductor radiation imaging device includes an array of pixel cells having an array of pixel detectors which directly generate charge in response to incident radiation and a corresponding array of individually-addressable pixel circuits. Each pixel circuit is associated with a respective pixel detector for accumulating charge directly resulting from radiation incident on the pixel detector and includes threshold circuitry and charge accumulation circuitry. The threshold circuitry is configured to discard radiation hits on the pixel detector outside a predetermined threshold range, and the charge accumulation circuit is configured to accumulate charge directly resulting from a plurality of successive radiation hits on the respective pixel detector within the predetermined threshold range.

Abstract: An imaging device comprises a semiconductor substrate including an array of pixel cells. Each pixel cell comprising an individually addressable pixel circuit for accumulating charge resulting from radiation incident on a pixel detector. The pixel circuit and the pixel detector can either be implemented on a single substrate, or on two substrates bonded together. The charge storage device can be a transistor, for example one of a pair of FET transistors connected as a cascade amplification stage. An imaging plane can be made up of one imaging device or a plurality of imaging devices tiled to form a mosaic. The imaging devices may be configured as a slot for certain applications, the slit or slot being scanned over the imaging plane. Control electronics can include addressing logic for addressing individual pixel circuits for reading accumulated charge from the pixel circuits.

Abstract: An imaging device comprises a semiconductor substrate including an array of pixel cells. Each pixel cell comprising an individually addressable pixel circuit for accumulating charge resulting from radiation incident on a pixel detector. The pixel circuit and the pixel detector can either be implemented on a single substrate, or on two substrates bonded together. The charge storage device can be a transistor, for example one of a pair of FET transistors connected as a cascade amplification stage. An imaging plane can be made up of one imaging device or a plurality of imaging devices tiled to form a mosaic. The imaging devices may be configured as a slot for certain applications, the slit or slot being scanned over the imaging plane. Control electronics can include addressing logic for addressing individual pixel circuits for reading accumulated charge from the pixel circuits.

Abstract: An imaging device comprises a semiconductor substrate including an array of pixel cells. Each pixel cell comprising an individually addressable pixel circuit for accumulating charge resulting from radiation incident on a pixel detector. The pixel circuit and the pixel detector can either be implemented on a single substrate, or on two substrates bonded together. The charge storage device can be a transistor, for example one of a pair of FET transistors connected as a cascade amplification stage. An imaging plane can be made up of one imaging device or a plurality of imaging devices tiled to form a mosaic. The imaging devices may be configured as a slot for certain applications, the slit or slot being scanned over the imaging plane. Control electronics can include addressing logic for addressing individual pixel circuits for reading accumulated charge from the pixel circuits.

Abstract: An imaging device comprises a semiconductor substrate including an array of pixel cells. Each pixel cell comprising an individually addressable pixel circuit for accumulating charge resulting from radiation incident on a pixel detector. The pixel circuit and the pixel detector can either be implemented on a single substrate, or on two substrates bonded together. The charge storage device can be a transistor, for example one of a pair of FET transistors connected as a cascade amplification stage. An imaging plane can be made up of one imaging device or a plurality of imaging devices tiled to form a mosaic. The imaging devices may be configured as a slot for certain applications, the slit or slot being scanned over the imaging plane. Control electronics can include addressing logic for addressing individual pixel circuits for reading accumulated charge from the pixel circuits.

Abstract: A semiconductor high-energy radiation imaging device having an array of pixel cells includes a semiconductor detector substrate and a semiconductor readout substrate. The semiconductor detector substrate includes an array of pixel detector cells, each of which directly generates charge in response to incident high-energy radiation. The semiconductor readout substrate includes an array of individually addressable pixel circuits, each of which is connected to a corresponding pixel detector cell to form a pixel cell. Each pixel circuit includes charge accumulation circuitry for accumulating charge directly resulting from high-energy radiation incident on a corresponding pixel detector cell, readout circuitry for reading the accumulated charge, and reset circuitry for resetting the charge accumulation circuitry. The charge accumulation circuitry has a charge storage capacity sufficient to store at least 1.