Patents by Inventor Rita J. Klein

Rita J. Klein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894305
    Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 6, 2024
    Inventors: Jordan D. Greenlee, John D. Hopkins, Rita J. Klein, Everett A. McTeer, Lifang Xu, Daniel Billingsley, Collin Howder
  • Publication number: 20230397424
    Abstract: A microelectronic device comprises a stack structure, a memory pillar, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The memory pillar extends through the stack structure and defines memory cells at intersections of the memory pillar and the conductive structures. The boron-containing material is on at least a portion of the conductive structures of the stack structure. Related methods and electronic systems are also described.
    Type: Application
    Filed: May 25, 2023
    Publication date: December 7, 2023
    Inventors: Jordan D. Greenlee, Everett A. McTeer, Rita J. Klein, John D. Hopkins, Nancy M. Lomeli, Xiao Li, Christopher R. Ritchie, Alyssa N. Scarbrough, Jiewei Chen, Sijia Yu, Naiming Liu
  • Publication number: 20230395149
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory block regions individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a void-space extending laterally-across individual of the memory-block regions. At least one of conductive or semiconductive material is formed in the void-space laterally-outward of individual of the channel-material strings. Conductive molybdenum-containing metal material is formed in the void-space directly against the at least one of the conductive or the semiconductive material and a conductive line comprising the conductive molybdenum-containing metal material is formed therefrom. The at least one of the conductive or the semiconductive material is of different composition from that of the conductive molybdenum-containing metal material.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 7, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, David Ross Economy, John D. Hopkins, Nancy M. Lomeli, Jiewei Chen, Rita J. Klein, Everett A. McTeer, Aaron P. Thurber
  • Patent number: 11812610
    Abstract: Electronic devices (e.g., semiconductor devices, which may be configured for 3D NAND memory devices), comprise pillars extending through a stack of alternating conductive tiers and insulative tiers. The conductive tiers, which may include control gates for access lines (e.g., word lines), include conductive rails along an outer sidewall of the conductive tiers, distal from the pillars extending through the conductive tiers. The conductive rails protrude laterally beyond outer sidewalls of the insulative tiers. The conductive rails increase the amount of conductive material that may otherwise be in the conductive tiers, which may enable the conductive material to exhibit a lower electrical resistance, improving operational performance of the electronic devices.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Rita J. Klein, Jordan D. Greenlee
  • Patent number: 11800706
    Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: October 24, 2023
    Inventors: Shuangqiang Luo, Indra V. Chary, Justin B. Dorhout, Rita J. Klein
  • Patent number: 11791268
    Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Christian George Emor, Travis Rampton, Everett Allen McTeer, Rita J. Klein
  • Publication number: 20230290721
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 14, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Jiewei Chen, Sijia Yu, Chieh Hsien Quek, Rita J. Klein, Nancy M. Lomeli
  • Patent number: 11742282
    Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Rita J. Klein, Everett A. McTeer, John D. Hopkins, Shuangqiang Luo, Song Kai Tan, Jing Wai Fong, Anurag Jindal, Chieh Hsien Quek
  • Patent number: 11705500
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
  • Publication number: 20230207458
    Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches.
    Type: Application
    Filed: October 12, 2022
    Publication date: June 29, 2023
    Inventors: Alyssa N. Scarbrough, David Ross Economy, Jay S. Brown, John D. Hopkins, Jordan D. Greenlee, Mithun Kumar Ramasahayam, Rita J. Klein
  • Publication number: 20230154856
    Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of 3-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: January 23, 2023
    Publication date: May 18, 2023
    Inventors: Jordan D. Greenlee, John D. Hopkins, Everett A. McTeer, Yiping Wang, Rajesh Balachandran, Rita J. Klein, Yongjun J. Hu
  • Publication number: 20230121315
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Applicant: Micron Technology, Inc.
    Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
  • Patent number: 11600630
    Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Nancy M. Lomeli, John D. Hopkins, Jiewei Chen, Indra V. Chary, Jun Fang, Vladimir Samara, Kaiming Luo, Rita J. Klein, Xiao Li, Vinayak Shamanna
  • Patent number: 11594495
    Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of ?-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins, Everett A. McTeer, Yiping Wang, Rajesh Balachandran, Rita J. Klein, Yongjun J. Hu
  • Publication number: 20230016742
    Abstract: Memory circuitry comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Charge-passage material is in the conductive tiers laterally-outward of the channel-material strings. Storage material is in the conductive tiers laterally-outward of the charge-passage material. At least one of AlOq, ZrOq, and HfOq is in the conductive tiers laterally-outward of the storage material. At least one of (a) and (b) is in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where, (a): MoOxNy, where each of “x” and “y” is from 0 to 4.0; and (b): MoMz, where “M” is at least one of W, a Group 7 metal, and a Group 8 metal; “z” being greater than 0 and less than 1.0. Metal material is in the conductive tiers laterally-outward of the at least one of the (a) and the (b). Memory cells are in individual of the conductive tiers.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Jordan D. Greenlee, Yongjun Jeff Hu, Rita J. Klein, Everett A. McTeer
  • Publication number: 20220310522
    Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of ?-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: March 23, 2021
    Publication date: September 29, 2022
    Inventors: Jordan D. Greenlee, John D. Hopkins, Everett A. McTeer, Yiping Wang, Rajesh Balachandran, Rita J. Klein, Yongjun J. Hu
  • Publication number: 20220310524
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first dielectric material; a second dielectric material separated from the first dielectric material; a memory cell string including a pillar extending through the first and second dielectric materials, the pillar including a portion between the first and second dielectric materials; an additional dielectric material contacting the portion of the pillar; a conductive material contacting the additional dielectric material; and a tungsten structure including a portion of tungsten contacting the conductive material, wherein a majority of the portion of tungsten is beta-phase tungsten.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Inventors: Jordan D. Greenlee, Rita J. Klein, Everett Allen McTeer, John Hopkins, David Ross Economy
  • Publication number: 20220310525
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first dielectric material; a second dielectric material separated from the first dielectric material; a memory cell string including a pillar extending through the first and second dielectric materials, the pillar including a portion between the first and second dielectric materials; and a tungsten material located between the first and second dielectric materials and separated from the portion of the pillar and the first and second dielectric materials by an additional dielectric material. The additional dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide. The additional dielectric material contacts the portion of the pillar and the tungsten material.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Inventors: Jordan D. Greenlee, Rita J. Klein, Everett Allen McTeer, John Hopkins
  • Publication number: 20220302032
    Abstract: A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 22, 2022
    Inventors: Jordan D. Greenlee, Christian George Emor, Luca Fumagalli, John D. Hopkins, Rita J. Klein, Christopher W. Petz, Everett A. McTeer
  • Publication number: 20220254727
    Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
    Type: Application
    Filed: April 26, 2022
    Publication date: August 11, 2022
    Inventors: Jordan D. Greenlee, Lifang Xu, Rita J. Klein, Xiao Li, Everett A. McTeer