Abstract: An arbiter connects a plurality of devices to a bus. The arbiter determines priority among the devices based on minimum access intervals associated with the devices and timers which keep track of the elapsed time since each device last had access to the bus. The timers can be configured to either count up from zero to the minimum access interval of each device or count down from the minimum access interval of each device to zero. The arbiter can also adjust the minimum access intervals of the various devices based upon factors such as the amount of data required by the device, the amount of data most recently received by the device and the transfer rate of the device. The arbiter thus optimizes bus usage while minimizing the likelihood of a given device not functioning based on an ability to access the bus due to contention with other devices.

Abstract: A power management unit is provided that includes a plurality of configuration registers for storing configuration information to set various operational parameters of the power management unit. A program register is mapped within the configuration space of the computer system and is utilized to store a value which sets the I/O address of the index register. The program register is written during the initialization of the power management unit, and may be associated with a predetermined default value. Once the program register has been set with a value indicating the I/O address of the index register, accesses to the configuration registers are achieved by first writing an offset value to the index register. Subsequently, configuration data may be written into or read out of a designated configuration register by executing an appropriate cycle to the address of the configuration data register, which may be mapped one word location beyond that of the index register.

Abstract: An arbiter connects a plurality of devices to a bus. The arbiter determines priority among the devices based on the relative need of the devices. Relative need is determined for each device based on the fullness of a buffer, such as a first-in first-out buffer, corresponding to each device. A gauge informs the arbiter of the fullness value for each buffer from which relative need, and hence priority, is calculated. In addition, the arbiter can incorporate the speed of each device's buffer into its priority determination. The relative device priorities can thus be changed dynamically as the buffers associated with the devices read and write data via the bus. Similarly, the relative priority of a given device can change when the device changes from an input mode to an output or from an output mode to an input mode.

Abstract: A power management unit that includes a software writable enable register for receiving an SMI enable bit when the generation of an immediate SMI is desired. When the enable bit is set, an SMI flag register causes the assertion of an SMI signal. The power management unit further includes a reason register that is also writable via software command. The reason register is written prior to the setup of the enable bit with a "reason value" indicative of the reason a pending SMI is being requested. The immediate system management interrupt source allows initiating software to indicate the reason it is requesting an SMI, and causes an associated SMI to be asserted with minimal latency. The immediate system management interrupt source further allows the system management interrupt service routine to quickly determine the reason for the immediate SMI, thereby allowing simplified and more efficient SMI service routines and further allowing greater flexibility in programming.

Abstract: A power management unit is provided that monitors various portions of a computer system and causes a reduction in the frequencies of the CPU clock signal and the system clock signal during a power conserving state. The power management unit includes a programmable counter for allowing the system designer to vary the length of a wake-up period that occurs in response to an assertion of a timer tick interrupt. An in-service register of an interrupt controller is coupled to the power management unit which thereby allows the power management unit to receive real-time information regarding whether a timer tick interrupt is currently being serviced by the microprocessor. When a timer tick status bit of the in-service register is set, the power management unit causes the CPU clock signal and the system clock signal to be driven at maximum frequencies. When the timer tick status bit clears, the programmable counter begins counting.

Abstract: A system and method for controlling a peripheral bus clock signal through a slave device are provided that accommodate a power conservation scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. Upon system reset, the BIOS boot code reads a configuration register MAXLAT within each alternate bus master. The contents of the configuration register are indicative of how often the particular master may require access to the peripheral bus. Upon reading the MAXLAT field of each master, the system sets a timer in accordance with the MAXLAT value corresponding to the master which requires the most frequent access to the peripheral bus. If the master requiring the peripheral bus most frequently specifies a maximum latency time of, for example, 2 microseconds, the system sets the timer to cycle (or trigger) every one microsecond (i.e., one-half of the specified maximum latency time).

Abstract: A system oscillator gating technique is provided for a power management unit of a computer system for controlling the application of power to a system oscillator. An output signal from the power management unit is provided to turn off the external system oscillator when the computer system is in a power-conserving suspend state and to turn on the external system oscillator on when the computer system resumes to a ready state. Counters are provided to control the latency of the output signal when the power management unit enters and exits the suspend state. This latency provides time for the microprocessor clock and/or other clock signals associated with the system oscillator to shut off prior to the oscillator shutdown and provides time for the oscillator to stabilize prior to the restarting of the clock signal. As a result, power consumption of the computer system may be reduced while proper clock generation for the computer system is maintained.

Abstract: A periodic system management interrupt (SMI) source is provided that includes a programmable timer for asserting an SMI a predetermined rate. A microprocessor is coupled to a periodic SMI source through a CPU local bus. The periodic SMI source may be programmed by executing an I/O write cycle which allows a count value and an enable bit to be loaded into an internal configuration register. When the enable bit is set, the programmable timer asserts a periodic system management interrupt at a fixed rate as determined by the count value within the configuration register. The periodic system management interrupt may be asserted, for example, at intervals of 16 milliseconds, 64 milliseconds, 245 milliseconds, 1 second, 16 seconds, or 1 minute. The periodic SMI source allows for the automatic generation of a periodic system management interrupt independently of software.

Abstract: The computer system includes an integrated processor coupled to a power management unit and at least one peripheral device. The integrated processor includes a bus interface unit that provides an interface to a high performance peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals.

Abstract: A system is disclosed for merging data from two separate registers at different locations in a computer system. A floppy drive controller is provided as part of a companion chip located separately from an IDE drive controller. Both controllers include a data register with the same address to make the system compatible with prior BIOS programs. The register in the floppy controller includes a DSK CHG bit as bit D7 of a direct input register (DIR), which is obtained from the DSK CHG# signal from the floppy drive. In the present invention, the DSK CHG# signal from the floppy drive is connected directly to the bus interface unit (BIU) of the integrated processor. The processor merges this signal with data bits D0-D6 of the IDE controller by determining the location of the IDE controller from the Address Control Register (ACR), which is determined during system initialization.

Abstract: A power management unit is provided that includes several states, each of which is associated with a different power management mode. Transitions between the states of the power management unit are dependent upon the type of activities detected. Upon reset of the computer system, the power management unit enters a ready state during which a CPU clock signal and a system clock signal are driven at their maximum frequencies. If no primary activities are detected over certain time periods, the power management unit successively transitions from the ready state to a doze state, then to a stand-by state, and then to a suspend state. During the doze state, the frequency of the CPU clock signal is slowed, and during the stand-by state, the CPU clock signal is stopped. During the suspend state, both the CPU clock signal and the system clock signal are stopped, and the power to selected circuit portions may be removed.

Abstract: A power management unit including a set of time-out counters and a software configurable state register is provided for managing power consumption within a computer system. Depending upon the state of the power management unit, a power control unit and a clock control unit are configured such that power may be applied or removed from certain components of the computer system and such that the frequencies of a CPU clock signal and a system clock signal may be raised or lowered. The power management unit includes a software configurable state register which allows system software, such as APM responsive software within the system BIOS, to control the state of the power management unit. When the power management unit is in a ready state during which the CPU clock signal and the system clock signal are driven at maximum frequencies and during which power is applied to all computer components, a time-out counter is activated to begin a first count down period.

Abstract: An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor such as activities of a floating-point coprocessing subunit. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an external power management unit. Power management decisions are made by an external power management unit.

Abstract: A computer system is provided that employs a disable technique which warns the user of a low battery condition when the user attempts to power-on the computer, and which prevents power from being applied to a primary portion of the computer system. A battery monitor is included for monitoring the voltage across the battery, and for asserting a control signal when the battery voltage drops below a certain threshold value. A control unit receives the control signal and accordingly prevents power from being applied to a primary computer subsystem when the computer system is turned on. Instead, when the user attempts to turn on the computer system when the low battery-capacity condition exists, the control unit causes a pulse generator to generate a signal that drives a speaker. An audible indication of the low power condition is thereby produced.