Abstract: A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a diffusion barrier layer on the first region, performing a hydrogen anneal such that the strain in the second region is relaxed.

Abstract: A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a diffusion barrier layer on the first region, performing a hydrogen anneal such that the strain in the second region is relaxed.

Abstract: One inventive aspect relates to a method of selective epitaxial growth of source/drain (S/D) areas. The method comprises providing a substrate of semiconductor material, the substrate comprising a first substrate area and a second substrate area, the first area comprising at least one gate stack. The method further comprises applying at least a poly-Si or poly-SiGe top layer on the substrate, the top layer being etchable with the same etch chemistry as the substrate. The method further comprises removing the poly-Si or poly-SiGe top layer from the first area of the substrate selectively towards the poly-Si or poly-SiGe top layer in the second substrate area. The method further comprises removing simultaneously the poly-Si or poly-SiGe top layer on the second substrate area and at least a part of the substrate in the S/D areas of the first substrate area selectively to the at least one gate stack. The method further comprises performing a selective epitaxial growth of S/D areas in the first substrate area.

Abstract: A method for the patterning of a plurality of fins in a MugFET device is provided. The method involves depositing at least one temporary pattern using photolithography. Further processing steps include a combination of depositing a conformal layer and spacer defined patterning of the conformal layer such that a very high density of fins can be achieved. The distance between the fins is no longer determined by photolithography, which is only used to define the temporary pattern which is removed in further processing, but instead by the thickness of the conformal layer, with all fins defined by spacers. Additionally an improved line edge roughness is achieved for the fins using the method.

Abstract: The present invention is related to a method for producing semiconductor devices from a semiconductor substrate, comprising providing a substrate having on its surface a number of elevated areas separated by areas which are at a lower level. Each elevated area has at its top surface a first layer of a material which is resistant to Chemical Mechanical Polishing (CMP). The method further comprises depositing a layer of a dielectric on top of the whole of said substrate, thereby filling the gaps between said elevated areas. The method further comprises depositing a second layer of a material which is resistant to CMP on top of the whole of said substrate. The method further comprises removing parts of the second CMP resistant layer and of dielectric layer. The method further comprises performing a CMP step and terminating the CMP step at the location of said first and second CMP resistant layers.

Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.

Abstract: A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.

Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.

Abstract: The present invention is related to a method for producing semiconductor devices from a semiconductor substrate, comprising providing a substrate having on its surface a number of elevated areas separated by areas which are at a lower level. Each elevated area has at its top surface a first layer of a material which is resistant to Chemical Mechanical Polishing (CMP). The method further comprises depositing a layer of a dielectric on top of the whole of said substrate, thereby filling the gaps between said elevated areas. The method further comprises depositing a second layer of a material which is resistant to CMP on top of the whole of said substrate. The method further comprises removing parts of the second CMP resistant layer and of dielectric layer. The method further comprises performing a CMP step and terminating the CMP step at the location of said first and second CMP resistant layers.

Abstract: A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.

Abstract: The present invention relates to methods for controlling the etching rate of CoSi2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schotky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.

Abstract: The present invention relates to methods for controlling the etching rate of CoSi.sub.2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schottky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.