Patents by Inventor Rita Van Hoof

Rita Van Hoof has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10451821
    Abstract: An example embodiment relates to a photonic integrated circuit device and a method for its manufacture. An example device includes a planar detector having at least one photodetector. The device may further include a waveguide layer arranged substantially parallel to the planar detector, the waveguide layer including a first integrated waveguide for guiding a first light signal. A cavity may be formed in the waveguide layer in a region spaced away from the edges of the waveguide layer such as to terminate the first integrated waveguide in that region. A first reflective surface may be provided in the cavity to reflect the first light signal guided by the first integrated waveguide toward a first photodetector of the planar detector.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 22, 2019
    Assignees: IMEC VZW, SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Tom Claes, Rita Van Hoof, Gillis Winderickx
  • Publication number: 20180156991
    Abstract: An example embodiment relates to a photonic integrated circuit device and a method for its manufacture. An example device includes a planar detector having at least one photodetector. The device may further include a waveguide layer arranged substantially parallel to the planar detector, the waveguide layer including a first integrated waveguide for guiding a first light signal. A cavity may be formed in the waveguide layer in a region spaced away from the edges of the waveguide layer such as to terminate the first integrated waveguide in that region. A first reflective surface may be provided in the cavity to reflect the first light signal guided by the first integrated waveguide toward a first photodetector of the planar detector.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 7, 2018
    Applicants: IMEC VZW, Samsung Electronics Co. Ltd.
    Inventors: Tom Claes, Rita Van Hoof, Gillis Winderickx
  • Patent number: 6130478
    Abstract: A polymer stud grid array for microwave circuits is proposed which includes an injection-molded, three-dimensional substrate that is fabricated from an electrically insulating polymer. The substrate includes a plurality of polymer studs which are arranged over the underside of the substrate and which are integrally formed with the substrate during the injection-molding process. Signal connections are formed on the studs which include an end surface that is capable of being soldered. Potential connections are formed on at least one of the studs. The potential connection also includes an end surface that is capable of being soldered. Striplines are also constructed which connect the studs to the microwave circuit. Each stripline includes a first structured metal layer disposed on the underside of the substrate, a dielectric layer disposed on the first metal layer and a second structured metal layer disposed on top of the dielectric layer.
    Type: Grant
    Filed: April 18, 1998
    Date of Patent: October 10, 2000
    Assignees: Siemens N.V., Interuniversitair Micro-Electronica-Centrum VZW
    Inventors: Ann Dumoulin, Marcel Heerman, Jean Roggen, Eric Beyne, Rita van Hoof
  • Patent number: 6122172
    Abstract: In order to achieve better dissipation of the heat losses, a polymer stud grid array in proposed havingan injection-molded, three-dimensional substrate (S) composed of an electrically insulating polymer,polymer studs (PS) which are arranged over the area on the underneath of the substrate (S) and are integrally formed during injection molding,external connections which are formed on the polymer studs (PS) by an end surface which can be soldered,conductor runs which are formed at least on the underneath of the substrate (S) and connect the external connections to internal connections,at least one heat sink (WL) which is partially coated during the injection molding of the substrate (S), and havingat least one chip or wiring element (VE) which is arranged on the heat sink (WL) and whose connections are electrically conductively connected to the internal connections.The new configuration is suitable in particular for power components or power modules in a polymer stud grid array package.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: September 19, 2000
    Assignees: Siemens NV, Interuniversitair Micro-Electronica-Centrum VZW
    Inventors: Ann Dumoulin, Marcel Heerman, Jean Roggen, Eric Beyne, Rita van Hoof
  • Patent number: 5929516
    Abstract: A structural shape has an injection molded, three-dimensional substrate composed of an electrically insulating polymer, polymer studs planarly arranged on the underside of the substrate and co-formed during injection molding, outside terminals formed on the polymer studs by a solderable end surface, interconnections fashioned at least on the underside of the substrate that connect the outside terminals to inside terminals, and at least one chip arranged on the substrate and whose terminals are electrically conductively connected to the inside terminals. The structural shape is suitable for single, few or multi chip module and unites the advantages of a ball grid array with the advantages of MID technology (Molded Interconnection Devices). The manufacture and metallization of the polymer studs can take place with minimal additional outlay in the framework of the method steps already required in the MID technology.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: July 27, 1999
    Assignees: Siemens N.V., Interuniversitair Micro-Electronica Centrum VZW
    Inventors: Marcel Heerman, Joost Wille, Jozef Van Puymbroeck, Jean Roggen, Eric Beyne, Rita Van Hoof