Patents by Inventor Rita Vos
Rita Vos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250208093Abstract: The present disclosure relates to a device for capturing an analyte having an affinity marker, including a first electrode, a second electrode, a porous material between the first and second electrodes, a first flow channel for flowing a fluid medium in between the first electrode and the porous material, and a second flow channel for flowing a fluid medium in between the second electrode and the porous material. The first and second electrodes generate an electrophoretic force steering, in operation, the analyte from the first flow channel into the porous material. The porous material is a porous monolith of titania, silica, or titania-silica comprising capture sites for binding to the affinity marker, having a contact area of at least 5 cm by 5 cm with each flow channel, a surface area larger than a surface area of the porous material, and a pore size of at least 100 nm.Type: ApplicationFiled: December 18, 2024Publication date: June 26, 2025Inventors: Camila Dalben Madeira Campos, Rita Vos, Lei Zhang, Kathrin Hoelz, Chengxun Liu
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Publication number: 20250208092Abstract: The present disclosure relates to a device for capturing a target molecule. The device includes a first electrode, a second electrode, a permeable structure between the first and second electrode, a first flow channel for flowing a fluid medium in between the first electrode and the permeable structure, and a second flow channel for flowing a fluid medium in between the second electrode and the permeable structure. The first and second electrodes are for generating an electrophoretic force steering, in operation, the target molecule from the first flow channel into the permeable structure, and the permeable structure includes capture sites for binding the target molecule.Type: ApplicationFiled: December 18, 2024Publication date: June 26, 2025Inventors: Camila Dalben Madeira Campos, Rita Vos, Lei Zhang, Kathrin Hoelz, Chengxun Liu
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Patent number: 11971385Abstract: A cyclic capillary electrophoresis device includes a capillary channel that forms a closed loop. The capillary channel comprises an inner half facing toward a space enclosed by the loop, where the inner half having an inner wall of first charge density, and an outer half facing away from the space enclosed by the loop, where the outer half having an inner wall surface of second charge density. A difference between the first and the second charge densities exists or can be turned on. The difference is configured to create a smaller average electroosmotic flow velocity in the inner half than in the outer half.Type: GrantFiled: September 11, 2020Date of Patent: April 30, 2024Assignees: Imec vzw, Katholieke Universiteit LeuvenInventors: Koen Martens, Chengxun Liu, Camila Dalben Madeira Campos, Rita Vos
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Publication number: 20210080427Abstract: A cyclic capillary electrophoresis device includes a capillary channel that forms a closed loop. The capillary channel comprises an inner half facing toward a space enclosed by the loop, where the inner half having an inner wall of first charge density, and an outer half facing away from the space enclosed by the loop, where the outer half having an inner wall surface of second charge density. A difference between the first and the second charge densities exists or can be turned on. The difference is configured to create a smaller average electroosmotic flow velocity in the inner half than in the outer half.Type: ApplicationFiled: September 11, 2020Publication date: March 18, 2021Inventors: Koen Martens, Chengxun Liu, Camila Dalben Madeira Campos, Rita Vos
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Patent number: 10746731Abstract: A method for immobilizing an analyte-recognizing molecule (1) on a surface (2?) functionalized with chemical groups Y1 suitable for reacting with a chemical group X2 of a coupling molecule (7) to form a reaction product comprising a chemical group Y2 suitable for reacting with the analyte-recognizing molecule (1), the method comprising the steps of: a) Providing the functionalized surface (2?), b) Contacting the functionalized surface (2?) with a solution (6) comprising simultaneously: i) The coupling molecule (7), and ii) The analyte-recognizing molecule (1).Type: GrantFiled: June 28, 2016Date of Patent: August 18, 2020Assignee: IMEC VZWInventors: Rita Vos, Karolien Jans, Tim Stakenborg
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Publication number: 20180149643Abstract: A method for immobilizing an analyte-recognizing molecule (1) on a surface (2?) functionalized with chemical groups Y1 suitable for reacting with a chemical group X2 of a coupling molecule (7) to form a reaction product comprising a chemical group Y2 suitable for reacting with the analyte-recognizing molecule (1), the method comprising the steps of: a) Providing the functionalized surface (2?), b) Contacting the functionalized surface (2?) with a solution (6) comprising simultaneously: i) The coupling molecule (7), and ii) The analyte-recognizing molecule (1).Type: ApplicationFiled: June 28, 2016Publication date: May 31, 2018Applicant: IMEC VZWInventors: Rita Vos, Karolien Jans, Tim Stakenborg
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Patent number: 9799523Abstract: The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 ?.Type: GrantFiled: October 12, 2015Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui OuYang, Jean-Luc Everaert, Laura Nyns, Rita Vos
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Publication number: 20160035575Abstract: The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 ?.Type: ApplicationFiled: October 12, 2015Publication date: February 4, 2016Inventors: Hui OuYang, Jean-Luc Everaert, Laura Nyns, Rita Vos
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Patent number: 9159582Abstract: The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 ?.Type: GrantFiled: October 30, 2008Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui OuYang, Jean-Luc Everaert, Laura Nyns, Rita Vos
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Patent number: 8828826Abstract: A method for manufacturing a transistor device is provided, the transistor device comprising a germanium based channel layer, the method comprising providing a gate structure on the germanium comprising channel layer provided on a substrate, the gate structure being provided between a germanium based source area and a germanium based drain area at opposite sides of the germanium comprising channel layer; providing a capping layer on the germanium based source and the germanium based drain area, the capping layer comprising Si and Ge; depositing a metal layer on the capping layer; performing a temperature step, thereby transforming at least part of the capping layer into a metal germano-silicide which is not soluble in a predetermined etchant adapted for dissolving the metal; selectively removing non-consumed metal from the substrate by means of the predetermined etchant; and providing a premetal dielectric layer.Type: GrantFiled: August 30, 2013Date of Patent: September 9, 2014Assignees: IMEC, Taiwan Semiconductor Manufacturing Company, Ltd., GLOBALFOUNDRIES, Inc.Inventors: Liesbeth Witters, Rita Vos, David Brunco, Marcus Johannes Henricus Van Dal
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Publication number: 20140061735Abstract: A method for manufacturing a transistor device is provided, the transistor device comprising a germanium based channel layer, the method comprising providing a gate structure on the germanium comprising channel layer provided on a substrate, the gate structure being provided between a germanium based source area and a germanium based drain area at opposite sides of the germanium comprising channel layer; providing a capping layer on the germanium based source and the germanium based drain area, the capping layer comprising Si and Ge; depositing a metal layer on the capping layer; performing a temperature step, thereby transforming at least part of the capping layer into a metal germano-silicide which is not soluble in a predetermined etchant adapted for dissolving the metal; selectively removing non-consumed metal from the substrate by means of the predetermined etchant; and providing a premetal dielectric layer.Type: ApplicationFiled: August 30, 2013Publication date: March 6, 2014Applicants: IMEC, Globalfoundries Inc., Taiwan Semiconductor Maunfacturing Company, Ltd.Inventors: Liesbeth Witters, Rita Vos, David Brunco, Marcus Johannes Henricus Van Dal
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Patent number: 8324116Abstract: A substrate treating method comprising a step of preparing a semiconductor substrate (W, 11) which has an oxide film (13, 14) containing at least one of a rare earth oxide and an alkaline earth oxide, at least a portion of the oxide film (13, 14) being exposed, and a rinse step of supplying the oxide film (13, 14) on the semiconductor substrate (W, 11) with a rinse liquid made of an alkaline chemical or an organic solvent. Preferably, the alkaline chemical is an alkaline aqueous solution having a pH of more than 7. Further, preferably, the organic solvent is a high concentration organic solvent having a concentration of substantially 100%.Type: GrantFiled: June 11, 2010Date of Patent: December 4, 2012Assignees: IMEC, Dainippon Screen Mfg. Co., Ltd.Inventors: Rita Vos, Paul Mertens, Tom Schram, Masayuki Wada
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Publication number: 20100317185Abstract: A substrate treating method comprising a step of preparing a semiconductor substrate (W, 11) which has an oxide film (13, 14) containing at least one of a rare earth oxide and an alkaline earth oxide, at least a portion of the oxide film (13, 14) being exposed, and a rinse step of supplying the oxide film (13, 14) on the semiconductor substrate (W, 11) with a rinse liquid made of an alkaline chemical or an organic solvent. Preferably, the alkaline chemical is an alkaline aqueous solution having a pH of more than 7. Further, preferably, the organic solvent is a high concentration organic solvent having a concentration of substantially 100%.Type: ApplicationFiled: June 11, 2010Publication date: December 16, 2010Inventors: Rita Vos, Paul Mertens, Tom Schram, Masayuki Wada
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Publication number: 20090223832Abstract: The present invention is related to a method and apparatus for cleaning a semiconductor substrate including on a surface of the substrate at least one structure comprising a first conducting or semiconducting material, surrounded by a layer of a second conducting or semiconducting material, said layer essentially extending over the totality of said surface, the first and second material being in physical contact, the method comprising the steps of: providing the substrate, positioning a counter-electrode facing the substrate surface, and supplying an electrolytic fluid to the space between the surface and the electrode, the counter-electrode acting as an anode in the galvanic cell defined by the substrate surface, the cleaning fluid and the counter-electrode.Type: ApplicationFiled: January 7, 2009Publication date: September 10, 2009Applicants: Interuniversitair Microelektronica Centrum vzw (IMEC), Katholieke Universiteit Leuven, K.U.LEUVEN R&DInventors: Sylvain Garaud, Rita Vos, Leonardus Leunissen, Paul Mertens
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Publication number: 20090117750Abstract: The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 ?.Type: ApplicationFiled: October 30, 2008Publication date: May 7, 2009Applicants: Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven, Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)Inventors: Hui OuYang, Jean-Luc Everaert, Laura Nyns, Rita Vos
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Patent number: 7521408Abstract: The present invention recites a composition comprising a first compound and a second compound. The first compound has the chemical formula ( 1a), wherein m, n and o are independently from each other equal to 2 or 3; wherein p is equal to 1 or 2; R being a chemical group with the chemical formula (1a?), wherein q is equal to 1, 2 or 3; wherein R1, R2 and R3 are independently selected from the group consisting of hydrogen and an organic group. The second compound has the chemical formula (1c). Metal ions can be present in the solution or in an external medium being contacted with the solution. The present invention can be used for cleaning a semiconductor substrate.Type: GrantFiled: December 12, 2005Date of Patent: April 21, 2009Assignees: Interuniversitair Microelektronica Centrum ( IMEC), Air Products and Chemicals Inc.Inventors: Rita Vos, Paul Mertens, Bernd Kolbesen, Albrecht Fester, Oliver Doll
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Patent number: 7432233Abstract: The invention relates to a method for cleaning semiconductor surfaces to achieve to removal of all kinds of contamination (particulate, metallic and organic) in one cleaning step. The method employs a cleaning solution for treating semiconductor surfaces which is stable and provokes less or no metal precipitation on the semiconductor surface.Type: GrantFiled: December 16, 2004Date of Patent: October 7, 2008Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Rita De Waele, Rita Vos
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Patent number: 7422019Abstract: The invention relates to a method for cleaning semiconductor surfaces to achieve to removal of all kinds of contamination (particulate, metallic and organic) in one cleaning step. The method employs a cleaning solution for treating semiconductor surfaces which is stable and provokes less or no metal precipitation on the semiconductor surface.Type: GrantFiled: June 27, 2006Date of Patent: September 9, 2008Assignee: Interuniversitair Microelektronica Centrum (IMEC) vzwInventors: Rita De Waele, Rita Vos
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Publication number: 20080191286Abstract: The present disclosure provides a dual workfunction semiconductor device and a method for manufacturing a dual workfunction semiconductor device. The method comprises providing a device on a first region and a device on a second region of a substrate. According to embodiments described herein, the method includes providing a dielectric layer onto the first and second region of the substrate, the dielectric layer on the first region being integrally deposited with the dielectric layer on the second region, and providing a gate electrode on top of the dielectric layer on both the first and second regions, the gate electrode on the first region being integrally deposited with the gate electrode on the second region.Type: ApplicationFiled: January 10, 2008Publication date: August 14, 2008Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shou-Zen Chang, Hong Yu Yu, Anabela Veloso, Rita Vos, Stefan Kubicek, Serge Biesemans, Raghunath Singanamalla, Anne Lauwers, Bart Onsia
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Patent number: 7160482Abstract: The present invention is related to a composition comprising an oxidizing compound and a complexing compound with the chemical formula wherein R1, R2, R3 and R4 are selected from the group consisting of H and any organic side chain. The oxidizing compound can be in the form of an aqueous solution. The complexing compound is for complexing metal ions. Metal ions can be present in the solution or in an external medium being contacted with the solution.Type: GrantFiled: December 21, 2001Date of Patent: January 9, 2007Assignees: IMEC vzw, Air Products and Chemicals, Inc.Inventors: Rita Vos, Paul Mertens, Albrecht Fester, Oliver Doll, Bernd Kolbesen