Abstract: Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.

Abstract: First transistor logic is arranged by a first logic provider in circuit form and provides a minimum of functionality of the semiconductor device employed to bring up the semiconductor device, wherein the minimum of functionality is encrypted using a first encryption key. Second transistor logic is arranged by a second logic provider, different than the first logic provider, in circuit form to include security keys capable to perform cryptographic capabilities using a second encryption key. The second transistor logic further includes functionality that completes the semiconductor device as a chip device and is ready to process secure communication signals.

Abstract: Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.

Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.

Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.

Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.

Abstract: Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.

Abstract: First transistor logic is arranged by a first logic provider in circuit form and provides a minimum of functionality of the semiconductor device employed to bring up the semiconductor device, wherein the minimum of functionality is encrypted using a first encryption key. Second transistor logic is arranged by a second logic provider, different than the first logic provider, in circuit form to include security keys capable to perform cryptographic capabilities using a second encryption key. The second transistor logic further includes functionality that completes the semiconductor device as a chip device and is ready to process secure communication signals.

Abstract: A system, having a stream cache and a storage. The stream cache includes a stream cache controller adapted to control or mediate input data transmitted through the stream cache; and a stream cache memory. The stream cache memory is adapted to both store at least first portions of the input data, as determined by the stream cache controller, and to further output the stored first portions of the input data to a processor. The storage is adapted to receive and store second portions of the input data, as determined by the stream cache controller, and to further transmit the stored second portions of the input data for output to the processor.