Patents by Inventor Ritesh Bhat

Ritesh Bhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230208380
    Abstract: An impedance matching network for a radio frequency (RF) transmission system can include first port for coupling to a first transistor differential pair. The network can further include a second port for coupling to a second tansistor differential pair. The network can further incluede a matching network connected to the port and the second port, the matching network comprised of a pair of coupled lines. Other aspects are described.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Ritesh Bhat, Steven Callender
  • Publication number: 20230198575
    Abstract: A wireless communication device can include a channel matching network. The channel matching network includes a pair of coupled lines coupled to the input port, and a capacitive element coupled between the pair of coupled lines and an antenna load.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Ritesh Bhat, Stefano Pellerano, Christopher Hull
  • Publication number: 20220416751
    Abstract: Impedance matching circuits, impedance matching elements, and radio communication circuits are provided in this disclosure. The impedance matching circuit may include a first impedance matching element which is configured to radio communication circuit may include a modulator configured to receive an unbalanced input signal from a first input, and couple the unbalanced input signal to a first output to match an impedance of the first output to a first impedance. It may further include a second impedance matching element coupled to the first input to receive the unbalanced input signal, the second impedance matching element configured to couple the unbalanced input signal to a second output to match an impedance of the second output to a second impedance. A terminal of the first output and a terminal of the second output may be coupled to provide a balanced output signal, and the coupling may match an output impedance of the impedance matching circuit based on the first impedance and the second impedance.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Ritesh A. BHAT, Woorim SHIN
  • Publication number: 20220407544
    Abstract: Radio communication circuits, radio transmitters, and methods are provided in this disclosure. The radio communication circuit may include a modulator configured to provide a first modulated signal including a carrier signal at a carrier frequency, and a second modulated signal including the carrier signal at the carrier frequency. The radio communication circuit may further include a phase shift generator configured to receive a first signal based on the first modulated signal and a second signal based on the second modulated signal. The phase shift generator of the radio communication circuit may further be configured to provide a predefined phase difference between the first signal and the second signal.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 22, 2022
    Inventors: Woorim SHIN, Ritesh A. BHAT, Chuanzhao YU, Stefano PELLERANO
  • Publication number: 20220200642
    Abstract: Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Abhishek AGRAWAL, Ritesh A. BHAT, Steven CALLENDER, Brent R. CARLTON, Christopher D. HULL, Stefano PELLERANO, Mustafijur RAHMAN, Peter SAGAZIO, Woorim SHIN
  • Patent number: 10873360
    Abstract: Systems, methods, and circuitries are disclosed for performing self-interference cancellation in a transceiver. In one example, a self-interference cancellation system includes a cancellation signal circuitry, cancellation circuitry, down-conversion circuitry, and an LO derivation circuitry. The cancellation signal circuitry is configured to use a cancellation transmit (TX) local oscillator (LO) signal to up-convert a baseband transmit leakage replica signal to generate a cancellation signal. The cancellation circuitry is configured to combine the cancellation signal with a received signal to generate a corrected received signal. The down-conversion circuitry is configured to use a receive (RX) LO signal to down-convert the corrected received signal to generate a baseband received signal. The LO derivation circuitry is configured to derive the cancellation TX LO signal and the RX LO signal from a common LO signal.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: December 22, 2020
    Assignee: INTEL CORPORATION
    Inventors: Ritesh Bhat, Stefano Pellerano, Brent Carlton
  • Publication number: 20200313716
    Abstract: Systems, methods, and circuitries are disclosed for performing self-interference cancellation in a transceiver. In one example, a self-interference cancellation system includes a cancellation signal circuitry, cancellation circuitry, down-conversion circuitry, and an LO derivation circuitry. The cancellation signal circuitry is configured to use a cancellation transmit (TX) local oscillator (LO) signal to up-convert a baseband transmit leakage replica signal to generate a cancellation signal. The cancellation circuitry is configured to combine the cancellation signal with a received signal to generate a corrected received signal. The down-conversion circuitry is configured to use a receive (RX) LO signal to down-convert the corrected received signal to generate a baseband received signal. The LO derivation circuitry is configured to derive the cancellation TX LO signal and the RX LO signal from a common LO signal.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Ritesh Bhat, Stefano Pellerano, Brent Carlton
  • Publication number: 20190190469
    Abstract: Circuits for power-combined power amplifier array are provided, the circuits comprising: an input splitter coupled to an input that provides a plurality of outputs; a plurality of power amplifier unit cells, each power amplifier unit cell coupled to a corresponding output of the input splitter and each power amplifier unit cell providing an output signal at an output of the power amplifier unit cell; and a power combiner having an output, a plurality of inputs, each input coupled to the output of a corresponding power amplifier unit cell, and a plurality of C-L-C-section equivalents, each having an input connected to a corresponding one of the plurality of inputs of the power combiner and an output connected to the output of the power combiner.
    Type: Application
    Filed: July 30, 2018
    Publication date: June 20, 2019
    Inventors: Ritesh Bhat, Harish Krishnaswamy
  • Patent number: 10063197
    Abstract: Circuits for power-combined power amplifier array are provided, the circuits comprising: an input splitter coupled to an input that provides a plurality of outputs; a plurality of power amplifier unit cells, each power amplifier unit cell coupled to a corresponding output of the input splitter and each power amplifier unit cell providing an output signal at an output of the power amplifier unit cell; and a power combiner having an output, a plurality of inputs, each input coupled to the output of a corresponding power amplifier unit cell, and a plurality of C-L-C-section equivalents, each having an input connected to a corresponding one of the plurality of inputs of the power combiner and an output connected to the output of the power combiner.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: August 28, 2018
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Ritesh Bhat, Harish Krishnaswamy
  • Patent number: 9698838
    Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Shreyas Sen, Ritesh Bhat, Yanjie Wang, Stefano Pellerano, Christopher Hull, Farhana Sheikh
  • Publication number: 20170187405
    Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 29, 2017
    Inventors: Shreyas Sen, Ritesh Bhat, Yanjie Wang, Stefano Pellerano, Christopher Hull, Farhana Sheikh
  • Publication number: 20170040956
    Abstract: Circuits for power-combined power amplifier array are provided, the circuits comprising: an input splitter coupled to an input that provides a plurality of outputs; a plurality of power amplifier unit cells, each power amplifier unit cell coupled to a corresponding output of the input splitter and each power amplifier unit cell providing an output signal at an output of the power amplifier unit cell; and a power combiner having an output, a plurality of inputs, each input coupled to the output of a corresponding power amplifier unit cell, and a plurality of C-L-C-section equivalents, each having an input connected to a corresponding one of the plurality of inputs of the power combiner and an output connected to the output of the power combiner.
    Type: Application
    Filed: March 5, 2015
    Publication date: February 9, 2017
    Inventors: Ritesh Bhat, Harish Krishnaswamy