Patents by Inventor Ritesh P. Turakhia

Ritesh P. Turakhia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8352818
    Abstract: A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: January 8, 2013
    Assignee: LSI Corporation
    Inventors: Sandeep Kumar Goel, Narendra B. Devta-Prasanna, Ritesh P. Turakhia
  • Publication number: 20100153795
    Abstract: A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 17, 2010
    Applicant: LSI Corporation
    Inventors: Sandeep Kumar Goel, Narendra B. Devta-Prasanna, Ritesh P. Turakhia
  • Patent number: 7171638
    Abstract: A method and computer program for screening defects in integrated circuit die includes steps of receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die and generating a test matrix from the quiescent current measurements for each die in the sample lot. A de-mixing matrix is computed from independent component analysis that models passing die in the sample lot. A matrix of sources is generated as a product of the test matrix and the de-mixing matrix. The matrix of sources is normalized to zero mean and unit variance. A statistical limit of the passing die in the sample lot is selected from each of the sources in the normalized matrix of sources to determine a maximum and a minimum quiescent current limit for each of the sources. The maximum and the minimum quiescent current limit for each of the sources is generated as output.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: January 30, 2007
    Assignee: LSI Logic Corporation
    Inventors: Ritesh P. Turakhia, Robert B. Benware