Abstract: A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. Each data beat is loaded into the registers in sequential order. A corresponding system valid bit is provided for each register and is set when the corresponding register is loaded. In the core domain, a corresponding set of core valid bit registers is set in response to the system valid bit registers being set. A data sampler monitors the core valid bits in sequential order and controls a multiplexor to select a corresponding one of the registers that contains valid data. The data sampler resets the core valid bits which in-turn reset the system valid bits to signal the completion of a data transfer across the asynchronous interface.

Abstract: A data processor (102) includes a first-in, first-out (FIFO) buffer (110) having a variable threshold. The FIFO buffer (110) has a plurality of entries (200) for storing at least a portion of a data block that is to be transmitted through the FIFO buffer (110). To allow data blocks of varying size to be transmitted at different data rates, a variable threshold value for determining a maximum fullness of the FIFO buffer (110) is automatically calculated by the data processor (102) for each data block. This allows the data block to be transmitted through the FIFO buffer (110) as a continuous data stream, without interruption, from the data processor (102) to a data consumer. The variable threshold value is appended to a first entry of the data block along with start bits to indicate a beginning of the data block. The FIFO buffer (110) may include read and write counters (208, 212) and a comparator (210) for comparing a difference between read and write pointers and the variable threshold value.