Patents by Inventor Ritesh Sojitra

Ritesh Sojitra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POWER-ON-RESET SIGNAL ISOLATION DURING LOWER POWER MODE
    Publication number: 20230205305
    Abstract: A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.
    Type: Application
    Filed: November 30, 2022
    Publication date: June 29, 2023
    Inventors: Venkateswar Kowkutla, Chunhua Hu, Raghavendra Santhanagopal, Kazunobu Shin, Charles Gerlach, Rejitha Nair, Ritesh Sojitra, Sai Rajaraman, Anthony Seely, Siva Srinivas Kothamasu, Varun Singh, John Apostol
  • Synchronized voltage scaling and device calibration
    Patent number: 9098438
    Abstract: A method is provided for scaling voltage in an integrated circuit. A calibration operation is performed on a functional module on the integrated circuit periodically at a rate T1. At least one parameter on the integrated circuit in monitored to determine when a performance threshold is reached. A change is initiated to an operating voltage for a portion of the integrated circuit in response to reaching the threshold. The rate of performing calibration operation is increased to a higher rate T2 for a window of time W in response to initiating the change in operating voltage, after which the rate of performing calibration is returned to the rate T1.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 4, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jose Luis Flores, Lewis Nardini, Ritesh Sojitra, Denis Roland Beaudoin
  • Synchronized Voltage Scaling and Device Calibration
    Publication number: 20120084575
    Abstract: A method is provided for scaling voltage in an integrated circuit. A calibration operation is performed on a functional module on the integrated circuit periodically at a rate T1. At least one parameter on the integrated circuit in monitored to determine when a performance threshold is reached. A change is initiated to an operating voltage for a portion of the integrated circuit in response to reaching the threshold. The rate of performing calibration operation is increased to a higher rate T2 for a window of time W in response to initiating the change in operating voltage, after which the rate of performing calibration is returned to the rate T1.
    Type: Application
    Filed: August 25, 2011
    Publication date: April 5, 2012
    Inventors: Jose Luis Flores, Lewis Nardini, Ritesh Sojitra, Denis Roland Beaudoin
  • Receive timing manager
    Publication number: 20060222132
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Application
    Filed: April 4, 2005
    Publication date: October 5, 2006
    Inventors: Denis Beaudoin, Ritesh Sojitra, Gregory Christison