Abstract: An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

Abstract: An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

Abstract: For the achievement of data transfer time reduction, removal of noise data, and analytical efficiency improvement in an ADC data processing function of a time-of-flight mass spectrometer, the mass spectrometer comprises a data acquisition circuit including: an ND converter; a signal intensity addition memory that stores data of ion signals such as a time range and the number of measurements and performs an addition process; a voltage value frequency addition memory that performs an addition process of frequencies of voltage values of the predetermined time range and the number of measurements and stores addition results; a threshold level computation circuit that computes a predetermined threshold level from the results in the memory; a compression memory that extracts only data exceeding the threshold level from the data in the signal intensity addition memory; and a counter that controls a measurement time for data acquisition and the operation of each circuit.

Abstract: In a foreign matter inspection apparatus for a semiconductor wafer, a PMT which detects reflection light, an amplifier which amplifies a signal detected by the PMT and in which response characteristics of amplification are controlled by a control signal, an A/D converter which converts the signal amplified by the amplifier into a predetermined code and outputs the code, a control circuit which generates a control signal based on information of the semiconductor wafer having a correlation with the reflection light, and a data processing circuit which detects a foreign matter on the semiconductor wafer based on the code output from the A/D converter are provided.

Abstract: An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

Abstract: For the achievement of data transfer time reduction, removal of noise data, and analytical efficiency improvement in an ADC data processing function of a time-of-flight mass spectrometer, the mass spectrometer comprises a data acquisition circuit including: an A/D converter; a signal intensity addition memory that stores data of ion signals such as a time range and the number of measurements and performs an addition process; a voltage value frequency addition memory that performs an addition process of frequencies of voltage values of the predetermined time range and the number of measurements and stores addition results; a threshold level computation circuit that computes a predetermined threshold level from the results in the memory; a compression memory that extracts only data exceeding the threshold level from the data in the signal intensity addition memory; and a counter that controls a measurement time for data acquisition and the operation of each circuit.

Abstract: In a data acquisition system of ADC system, a log amplifier is provided at the pre-stage of an A/D converter, a signal amplified by the log amplifier having a nonlinear input-output characteristic is A/D-converted, and an adding operation of data is performed while reconverting a voltage value data which is converted to a nonlinear characteristic to data with a linear scale according to a table memory for reverse-log conversion. A known voltage value is inputted into the log amplifier to perform measurement, and calibration of the table memory is performed by storing the voltage value and the voltage value data after A/D-converted.

Abstract: An inspection apparatus and method are disclosed for inspecting a magnetic disk or a magnetic head. A first reference signal generating source generates reference signals of a controllable oscillating frequency, and a signal switching means selects either a reference signal or test data reproduced by the magnetic head. Factors such as offsets and gain differentials among signal distribution paths, phase shifts of sampling clocks supplied to a plurality of AID converters, and frequency-dependence of the transfer function and phase response of signal paths are identified so that errors due to these factors can be detected. Based on the detected values of these factors and errors, reference signals are utilized to compensate test data errors.

Abstract: In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

Abstract: In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

Abstract: In order to easily perform a timing test on a memory interface included in a semiconductor device so as to satisfy a restriction on latency, the present invention provides a semiconductor device with the memory interface including: a clock output terminal that outputs a clock signal associated with an operation of a memory connected to the memory interface; a command terminal that outputs a command signal associated with control of a state of the memory; a data terminal that exchanges a data signal with the memory; and a data strobe terminal that exchanges a data strobe signal for establishing the data signal. This semiconductor device includes a testing terminal that outputs in advance a signal for starting a test on the memory interface apart from the command signal.

Abstract: In a foreign matter inspection apparatus for a semiconductor wafer, a PMT which detects reflection light, an amplifier which amplifies a signal detected by the PMT and in which response characteristics of amplification are controlled by a control signal, an A/D converter which converts the signal amplified by the amplifier into a predetermined code and outputs the code, a control circuit which generates a control signal based on information of the semiconductor wafer having a correlation with the reflection light, and a data processing circuit which detects a foreign matter on the semiconductor wafer based on the code output from the A/D converter are provided.

Abstract: The present invention relates to a data processing device for mass spectrometry, in which measurements are performed in a high dynamic range without causing an overrange in an A/D converter in any TOF scan. A data acquisition circuit of a mass spectrometer includes an amplitude value computing circuit which measures and stores a maximum amplitude value of an ion detection signal, a gain control circuit for determining and setting a gain amount for the next measurement, and others. From the immediately preceding TOF scan data or TOF scan data plural times before, the maximum amplitude value of the ion detection signal is extracted. Then, before the next TOF scan, an optimum gain amount is determined based on the extracted maximum amplitude value to adjust the gain of the input signal, and the ion signal is sampled in the A/D converter.

Abstract: A semiconductor device according to the present invention has a liquid crystal driver circuit, and when gray-scale voltage thereof is tested, the gray-scale voltage (Vx) generated in a gray-scale voltage generator circuit provided therein is compared with reference voltage (e.g., Vx+?V) generated for testing the gray-scale voltage and the test result is output as binarized voltage from external terminals of the semiconductor device. This can speed up the gray-scale voltage test even in the case of higher gray scale in the liquid crystal driver circuit or increased number of output terminals of the semiconductor device. Therefore, it becomes possible to reduce the time and cost required for the test.

Abstract: In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

Abstract: A problem, which one of the inventions included in the present application solves, is to provide a semiconductor device that can simultaneously test a plurality of output pins by less channels of a semiconductor test equipment in number than the integrated output pins of the semiconductor device. Representative one of the inventions has such a configuration that an LCD driver, which is the semiconductor device having a function of driving a gate line of a liquid crystal display panel, comprises: an exclusive-OR circuit for inverting polarities of positive and negative voltages for driving the gate line; a tri-state type inverter circuit capable of changing and controlling, to a high-impedance state, an output circuit for driving the gate line; and at least one of test control terminals TEST for controlling the exclusive-OR circuit and the tri-state type inverter circuit.

Abstract: A semiconductor device having a liquid crystal driving circuit is disclosed. The driving circuit includes a digital functional unit and an analog functional unit. The digital functional unit is comprised of a display controller and a display data storage RAM, while the analog functional unit is made up of a gradation voltage generating circuit and a gradation voltage selecting circuit. The digital and analog function units are functionally divided from each other and testing of the digital function and testing of the analog function unit are performed in an overlapping manner independently from each other.

Abstract: In a data acquisition system of ADC system, a log amplifier is provided at the pre-stage of an A/D converter, a signal amplified by the log amplifier having a nonlinear input-output characteristic is A/D-converted, and an adding operation of data is performed while reconverting a voltage value data which is converted to a nonlinear characteristic to data with a linear scale according to a table memory for reverse-log conversion. A known voltage value is inputted into the log amplifier to perform measurement, and calibration of the table memory is performed by storing the voltage value and the voltage value data after A/D-converted.

Abstract: A magnetic characteristic inspecting apparatus including a plurality of disk rotating devices or a plurality of magnetic heads include a unit for switching output signals of write signal production units or allocating the output signals to the magnetic heads, a unit for switching signals read from the magnetic heads or allocating the read signals to measurement resources, and a unit for selecting any of the disk rotating devices synchronously with which the measurement resources will perform measurement. The write signal production units and measurement resources are shared among inspections of the plurality of disk rotating devices or the plurality of heads.

Abstract: In order to easily perform a timing test on a memory interface included in a semiconductor device so as to satisfy a restriction on latency, the present invention provides a semiconductor device with the memory interface including: a clock output terminal that outputs a clock signal associated with an operation of a memory connected to the memory interface; a command terminal that outputs a command signal associated with control of a state of the memory; a data terminal that exchanges a data signal with the memory; and a data strobe terminal that exchanges a data strobe signal for establishing the data signal. This semiconductor device includes a testing terminal that outputs in advance a signal for starting a test on the memory interface apart from the command signal.