Abstract: Embodiments of apparatuses, methods, and systems for flexible provisioning of coherent memory address decoders in hardware are disclosed. In an embodiment, an apparatus includes a plurality of address decoders and a plurality of configuration storage locations. Each of the configuration storage locations corresponds to one of the plurality of address decoders to configure the corresponding one of the plurality of address decoders to decode based on a corresponding one of a plurality of decode rules. Each of the plurality of configuration storage locations is allocated to one of a plurality of memory tiers.

Abstract: Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises at least one of: a repeater circuitry and a fanout structure in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality.

Abstract: A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.

Abstract: Techniques for shared data prefetch are described. An exemplary instruction for shared data prefetch includes at least one field for an opcode, at least one field for a source operand to provide a memory address at least a byte of data, wherein the opcode is to indicate that circuitry is to fetch of a line of data from memory at the provided address that contains the byte specified with the source operand and store that byte in at least a cache local to a requester, wherein the byte of data is to be stored in a shared state.

Abstract: Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.

Abstract: Examples include techniques associated with mapping system memory physical addresses to proximity domains. Examples include mapping system memory physical addresses for a memory coupled with a multi-die system to proximity domains that include cores of a multi-core processor and the associated level 3 (L3) cache for use by each core included in a respective proximity domain. The mapping is to facilitate cache line ownership of a cache line in an L3 cache by an input/output device or agent located on a separate die from the multi-core processor.

Abstract: In one embodiment, a system includes an (input/output) I/O domain and a compute domain. The I/O domain includes an I/O agent and a I/O domain caching agent. The compute domain includes a compute domain caching agent and a compute domain cache hierarchy. The I/O agent issues an ownership request to the compute domain caching agent to obtain ownership of a cache line in the compute domain cache hierarchy. In response to the ownership request, the compute domain caching agent places the cache line in the compute domain cache hierarchy in a placeholder state. The placeholder state reserves the cache line for performance of a write operation by the I/O agent. The compute domain caching agent writes data received from the I/O agent to the cache line in the compute domain cache hierarchy and transitions the state of the cache line out of the placeholder state.

Abstract: A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.

Abstract: A fabric controller is provided for a coherent accelerator fabric. The coherent accelerator fabric includes a host interconnect, a memory interconnect, and an accelerator interconnect. The host interconnect communicatively couples to a host device. The memory interconnect communicatively couples to an accelerator memory. The accelerator interconnect communicatively couples to an accelerator having a last-level cache (LLC). An LLC controller is provided that is configured to provide a bias check for memory access operations on the fabric.

Abstract: Systems and methods are described herein for providing single sign-on capabilities. In some embodiments, an intermediate endpoint of a service provider receives, from a user device, an http_post message including security data provided by an identity provider. In some embodiments, the intermediate endpoint retrieves relay state data specific to the identity provider and transmits the security data and the relay state data to the user device. The user device then transmits the security data and relay state data to an authentication endpoint of the service provider. The authentication endpoint verifies that the SAML response indicated the user was authenticated by an identity provider. A URL may be retrieved from the relay state data and the user device's web browser is redirected to the URL to provide access to one or more services of the service provider.

Abstract: The present disclosure provides compositions comprising colloidal matter in solvent, employed for crackle formation when exposed to surface of a substrate. The said compositions crackle spontaneously without any external stimuli when exposed to the substrate surface as a film. The present disclosure also relates to substrates having a film by exposure to said composition and a method of preparing said substrate. The present disclosure also relates to patterned substrates fabricated with material or energy inputs deposited in template formed by crackling of the film and a method of preparing said patterned substrate and a kit for obtaining such substrates. The present disclosure also relates to using the said substrates for various applications specifically in the field of electronics or optoelectronics.

Abstract: A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.

Abstract: Techniques are provided for low-latency, high bandwidth graphics accelerator die and memory system. In an example, a graphics accelerator die can include a plurality of memory blocks for storing graphic information, a display engine configured to request and receive the graphic information from the plurality of memory blocks for transfer to a display, a graphics engine configured to generate and transfer the graphic information to the plurality of memory blocks, and a high-bandwidth, low-latency isochronous fabric configured to arbitrate the transfer and reception of the graphic information.

Abstract: The present disclosure provides compositions comprising colloidal matter in solvent, employed for crackle formation when exposed to surface of a substrate. The said compositions crackle spontaneously without any external stimuli when exposed to the substrate surface as a film. The present disclosure also relates to substrates having a film by exposure to said composition and a method of preparing said substrate. The present disclosure also relates to patterned substrates fabricated with material or energy inputs deposited in template formed by crackling of the film and a method of preparing said patterned substrate and a kit for obtaining such substrates. The present disclosure also relates to using the said substrates for various applications specifically in the field of electronics or optoelectronics.

Abstract: Embodiments of the present disclosure relate to a system and method to detect hydrogen leakage. The system uses a fluid sensing apparatus (104), a light source (120) and a photo detector (122). The nano-crystallized palladium gratings (118) are used as sensors which expand sensitively upon exposure to the hydrogen (H2). In an embodiment, the hydrogen sensing is based on monitoring the changes in the diffraction efficiency (DE) which is defined as the ratio of the first and the zeroth order diffracted beam intensities. The diffraction efficiency undergoes large and sudden changes as the nano-crystalline Pd grating becomes highly disordered due to PdHx formation. An embodiment of the present disclosure also relates to producing nanocrystalline Pd diffraction gratings along with the design and fabrication aspects of an indigenously built optical diffraction cell for H2 sensing.