Abstract: A CMOS semiconductor device which avoids latchup in the powerup mode as well as in the normal operating mode is provided. The device is provided with an on-chip back bias generator which greatly reduces the possibility of forward biasing parasitic NPNP transistors in normal operation. During the powerup mode, before the backbias voltage becomes effective, a clamp diode provided in integrated form outside a guardring surrounding the circuit elements is effective to clamp a large negative voltage that may be created by a "hot-socket" connection to an output. In a modified form of the invention, a junction field effect transistor is provided to prevent forward biasing of the parasitic transistors in a somewhat different manner.

Abstract: A field effect transistor has improved punch-through resistance by the implantation of a dose of ions through the center of the active area. The energy of the dose is such that the ion concentration peaks at the depth most susceptible to punch-through. The threshold voltage of the transistor is set by the combination of a lower than normal threshold implant and the tail concentration of the blocking implant.