Patents by Inventor Ritwik Chatterjee
Ritwik Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10922151Abstract: Methods, systems, and computer-readable storage media for detecting and managing events from data of an Internet-of-Things (IoT) network, and actions can include receiving a first call from a first application, the first call including timeseries data from one or more IoT devices in a first IoT network, retrieving a rule set for processing the timeseries data, and determining that an anomaly is represented in the timeseries data based on the rule set, and in response, generating an event, the event having a configuration that is customized by an enterprise associated with the first application, executing an event workflow to transition the event between states, and transmitting an event response to the first application.Type: GrantFiled: July 3, 2018Date of Patent: February 16, 2021Assignee: SAP SEInventors: Harry Lube, Ritwik Chatterjee, Aparajita
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Publication number: 20200012541Abstract: Methods, systems, and computer-readable storage media for detecting and managing events from data of an Internet-of-Things (IoT) network, and actions can include receiving a first call from a first application, the first call including timeseries data from one or more IoT devices in a first IoT network, retrieving a rule set for processing the timeseries data, and determining that an anomaly is represented in the timeseries data based on the rule set, and in response, generating an event, the event having a configuration that is customized by an enterprise associated with the first application, executing an event workflow to transition the event between states, and transmitting an event response to the first application.Type: ApplicationFiled: July 3, 2018Publication date: January 9, 2020Inventors: Harry Lube, Ritwik Chatterjee, Aparajita
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Patent number: 8586474Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.Type: GrantFiled: March 4, 2011Date of Patent: November 19, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Ritwik Chatterjee, Eddie Acosta, Sam S. Garcia, Varughese Mathew
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Patent number: 8581383Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.Type: GrantFiled: September 8, 2010Date of Patent: November 12, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Scott K. Pozder, Ritwik Chatterjee
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Patent number: 8003517Abstract: A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over a portion of the substrate; (c) removing the second portion of the seed layer; and (d) depositing a metal (215) over the first portion of the seed layer by an electroless process.Type: GrantFiled: May 29, 2007Date of Patent: August 23, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Varughese Mathew, Eddie Acosta, Ritwik Chatterjee, Sam S. Garcia
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Patent number: 7993971Abstract: A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer.Type: GrantFiled: December 28, 2007Date of Patent: August 9, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Ritwik Chatterjee, Eddic Acosta, Varughese Mathew
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Publication number: 20110151663Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.Type: ApplicationFiled: March 4, 2011Publication date: June 23, 2011Inventors: Ritwik Chatterjee, Eddie Acosta, Sam S. Garcia, Varughese Mathew
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Patent number: 7932175Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.Type: GrantFiled: May 29, 2007Date of Patent: April 26, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Ritwik Chatterjee, Eddie Acosta, Sam S. Garcia, Varughese Mathew
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Publication number: 20100327440Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.Type: ApplicationFiled: September 8, 2010Publication date: December 30, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: SCOTT K. POZDER, RITWIK CHATTERJEE
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Patent number: 7811932Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.Type: GrantFiled: December 28, 2007Date of Patent: October 12, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Scott K. Pozder, Ritwik Chatterjee
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Patent number: 7807572Abstract: A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.Type: GrantFiled: January 4, 2008Date of Patent: October 5, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Varughese Mathew, Eddie Acosta, Ritwik Chatterjee, Sam S. Garcia
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Patent number: 7799678Abstract: A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.Type: GrantFiled: January 30, 2008Date of Patent: September 21, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Thomas J. Kropewnicki, Ritwik Chatterjee, Kurt H. Junker
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Patent number: 7763538Abstract: A method is provided for creating a barrier layer (217) on a substrate comprising a dielectric layer (203) and a metal interconnect (211). In accordance with the method, the substrate is treated with a first plasma comprising helium, thereby forming a treated substrate. The treated substrate is then exposed to a second plasma selected from the group consisting of oxidizing plasmas and reducing plasmas. Next, a barrier layer is created on the treated substrate.Type: GrantFiled: January 10, 2006Date of Patent: July 27, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Michael D. Turner, Ritwik Chatterjee, Stanley M. Filipiak
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Patent number: 7579258Abstract: A semiconductor device and method has interconnects with adjoining reservoir openings. A dielectric layer is formed as part of an uppermost of the one or more interconnect layers. Openings formed in the dielectric layer result in modified portions of the dielectric layer along portions of sidewalls of the openings. The openings are filled with a conductive material, such as metal. An exposed portion of the dielectric layer is removed to form protruding pads of the conductive material extending above the dielectric layer. Reservoir openings are formed adjacent the protruding pads by removing the modified portions of the dielectric layer. When the semiconductor device is bonded with another device, either a wafer or a die, laterally flowing metal collects in the reservoir openings and ensures that a reliable electrical connection is made between the semiconductor device and the other device.Type: GrantFiled: January 25, 2006Date of Patent: August 25, 2009Assignee: Freescale Semiconductor, Inc.Inventor: Ritwik Chatterjee
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Patent number: 7572723Abstract: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.Type: GrantFiled: October 25, 2006Date of Patent: August 11, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Varughese Mathew, Eddie Acosta, Ritwik Chatterjee, Sam S. Garcia
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Publication number: 20090191708Abstract: A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.Type: ApplicationFiled: January 30, 2008Publication date: July 30, 2009Inventors: Thomas J. Kropewnicki, Ritwik Chatterjee, Kurt H. Junker
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Publication number: 20090176366Abstract: A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.Type: ApplicationFiled: January 4, 2008Publication date: July 9, 2009Inventors: Varughese Mathew, Eddie Acosta, Ritwik Chatterjee, Sam S. Garcia
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Publication number: 20090170246Abstract: A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Inventors: Ritwik Chatterjee, Eddic Acosta, Varughese Mathew
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Publication number: 20090166888Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Inventors: Scott K. Pozder, Ritwik Chatterjee
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Publication number: 20080299762Abstract: A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over a portion of the substrate; (c) removing the second portion of the seed layer; and (d) depositing a metal (215) over the first portion of the seed layer by an electroless process.Type: ApplicationFiled: May 29, 2007Publication date: December 4, 2008Inventors: Varughese Mathew, Eddie Acosta, Ritwik Chatterjee, Sam S. Garcia