Abstract: A method for executing instructions in a data processor and improvements to data processor design, which combine the advantages of regular processor architecture and Very Long Instruction Word architecture to increase execution speed and ease of programming, while reducing power consumption. Instructions each consisting of a number of operations to be performed in parallel are defined by the programmer, and their corresponding execution unit controls are generated at compile time and loaded prior to program execution into a dedicated array in processor memory. Subsequently, the programmer invokes reference instructions to call these defined instructions, and passes parameters from regular instructions in program memory. As the regular instructions propogate down the processor's pipeline, they are replaced by the appropriate controls fetched from the dedicated array in processor memory, which then go directly to the execution unit for execution.

Abstract: A method for insertion of a dynamic number of implicit nop instructions by the microprocessor at run-time. The implicit nop instructor is a no operation instruction which is executed by the microprocessor without placing an actual nop instruction in the program itself. The method of the present invention enables the appropriate number of implicit nop instructions to be automatically calculated and executed for every occurrence of a multi-cycle instruction. Hereinafter, the term automatically refers to a process which occurs without the direct intervention of the programmer or higher-language compiler. The appropriate number of implicit nop instructions is automatically calculated by the microprocessor, by subtracting the number of IDSI from the total number of delay-slots which are required. The number of IDSI is preferably determined by the assembler, and then made available to the microprocessor.