Abstract: A system for management of storage devices includes compatibility with either or both of COM/RS232 port and USB port connectivity using, for example, Fibre Channel (FC) signal transmission. A USB to serial RS232 bridge device allows a storage processor (SP) to communicate with an COM/RS232 port of a universal asynchronous receiver/transmitter (UART) coupled to downstream disk array enclosures (DAEs) to provide DAE management information without the need to modify the connection of the switch to the DAEs, which may include FC interconnects. The output from an COM/RS232 port on an SP interface and the RS232 output on the USB to Serial bridge device may be muxed at the UART, and the output signal therefrom diplexed with a high frequency differential signal and transmitted to one or more of the downstream DAEs as an FC diplexed signal.

Abstract: An optimized memory refresh scheme controls and reduces instantaneous power consumption and power-related noise during DRAM refresh. In the optimized refresh implementation the DRAM is refreshed using a selectable overlap Column Address Select (CAS) before Row Address Select (RAS) refresh mode. A refresh interface between a host port and the memory system is over two bussed signals comprised of a Refresh Enable signal (Refresh.sub.-- Enable) and a Refresh Strobe pulse train (Refresh.sub.-- Strobe). Refresh.sub.-- Enable is issued by the host port to define a refresh operation. Refresh.sub.-- Strobe is a pulse train generated by the host port which is used as a clock for a sequential refresh sequencer. A refresh sequencer issues selectably timed column address refresh and row address refresh signals according to which the memory banks can all be selectably refreshed substantially in parallel, or with a predetermined selected level of overlap.

Abstract: A modular memory array configuration uses a combinatorial decoding device (decoder), instead of straight buffering, to effect optimal delivery of control and address signals. Each port accessing memory on the array drives a single copy of address and control signals, plus bank select signals, over a shared interface to the decoder. Bank select controls the decoder which drives the address and control to only the accessed bank. Address and control signals to all banks but the accessed bank, are pulled up (inactive) with resistors on the memory array. For N banks, log2 N bank select bits are needed. The decoder device does not need to be clocked and therefore avoids problems associated with selecting between and providing asynchronous or redundant clocks for a multi-ported shared memory with ports independent of and asynchronous to one another.