Abstract: Systems, devices, and methods for automating laboratory protocols utilizing cooperative efforts between differing components including fluidics, agitation and thermal control for processing a wide variety of disparate laboratory protocols are provided. In one aspect, a sample processing module is provided, including a housing configured to accommodate a pre-identified sample process, a temperature input capable of interfacing with a temperature controller, a fluid input capable of interfacing with an input fluid controller, a fluid output capable of interfacing with an output fluid controller, and a standardized agitation connector capable of interfacing with an agitator. A control system interfaces with the temperature input, fluid input, fluid output, and agitation connector to enable the system to perform laboratory protocols that require complex, sequential fluidic steps in association with the temperature and agitation control.

Abstract: A random access memory including an array of memory cells configured to store memory cell data, a first circuit, and a second circuit. The first circuit is configured to compare test data and memory cell data to obtain comparison results. The second circuit is configured to compress the comparison results and store the compressed comparison results.

Abstract: Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one or all the devices sharing a given set of test signals. By sharing test signals between multiple devices, the level of parallel testing may be increased without increasing the pin count and complexity of memory testers and probe cards.

Abstract: A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is configured to control the first memory cells. The second voltage source is configured to control the second memory cells. Also, the first voltage source is configured to be trimmed independently of the second voltage source to provide a first voltage that reduces leakage from the first memory cells and the second voltage source is configured to be trimmed independently of the first voltage source to provide a second voltage that reduces leakage from the second memory cells.

Abstract: Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one or all the devices sharing a given set of test signals. By sharing test signals between multiple devices, the level of parallel testing may be increased without increasing the pin count and complexity of memory testers and probe cards.

Abstract: A random access memory including an array of memory cells configured to store memory cell data, a first circuit, and a second circuit. The first circuit is configured to compare test data and memory cell data to obtain comparison results. The second circuit is configured to compress the comparison results and store the compressed comparison results.

Abstract: A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is configured to control the first memory cells. The second voltage source is configured to control the second memory cells. Also, the first voltage source is configured to be trimmed independently of the second voltage source to provide a first voltage that reduces leakage from the first memory cells and the second voltage source is configured to be trimmed independently of the first voltage source to provide a second voltage that reduces leakage from the second memory cells.