Abstract: A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.

Abstract: A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.