Patents by Inventor Rob Verity

Rob Verity has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7062733
    Abstract: Sub-sampled signals are compared to determine time delay, calibration of delay elements, and other precise time domain measurements, based on properties of aliased signals produced by the sub-sampling. In one embodiment, flip-flops sub-sample an input signal and a delayed signal. A counter measures time delay between edges in the sub-sampled input and sub-sampled delayed signal. The time delay is determined and averaged over a measurement window, and then scaled to determine an amount of delay of the delayed signal. Means to calibrate a delay element inside a measurement device (e.g., Bit Error Ratio Tester), utilizing sub-sampling techniques to achieve precise measurements very quickly and without the need for factory calibration.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: June 13, 2006
    Assignee: SyntheSys Research, Inc.
    Inventors: Andrei Poskatcheev, Tom Helmer, Rob Verity