Abstract: A programmable effects system for graphical user interfaces is disclosed. One embodiment comprises adjusting a graphical user interface in response to a tilt of a device. In this way, a graphical user interface may display a parallax effect in response to the device tilt.

Abstract: A programmable effects system for graphical user interfaces is disclosed. One embodiment comprises adjusting a graphical user interface in response to a tilt of a device. In this way, a graphical user interface may display a parallax effect in response to the device tilt.

Abstract: A programmable effects system for graphical user interfaces is disclosed. One embodiment comprises adjusting a graphical user interface in response to a tilt of a device. In this way, a graphical user interface may display a parallax effect in response to the device tilt.

Abstract: A method of forming a waveguide for a self-aligned Mach-Zehnder-Interferometer. The method includes forming a waveguide on a substrate and providing a first mask with a first opening exposing a first width and a pair of second widths towards opposite sides of the first width. Additionally, the method includes doping a first dopant of a first concentration through the first opening into a first thickness of the waveguide to form a first semiconducting phase thereof. The method includes providing a second mask with a second opening exposing part of the waveguide and doping a second dopant of a second concentration through the second opening into the part of the waveguide to form a second semiconductor phase thereof sharing a boundary with the first semiconducting phase to form a PN junction across the boundary. The boundary is allowed to vary with a margin of tolerance within the first width.

Abstract: A method of forming a waveguide for a self-aligned Mach-Zehnder-Interferometer. The method includes forming a waveguide on a substrate and providing a first mask with a first opening exposing a first width and a pair of second widths towards opposite sides of the first width. Additionally, the method includes doping a first dopant of a first concentration through the first opening into a first thickness of the waveguide to form a first semiconducting phase thereof. The method includes providing a second mask with a second opening exposing part of the waveguide and doping a second dopant of a second concentration through the second opening into the part of the waveguide to form a second semiconductor phase thereof sharing a boundary with the first semiconducting phase to form a PN junction across the boundary. The boundary is allowed to vary with a margin of tolerance within the first width.

Abstract: A programmable effects system for graphical user interfaces is disclosed. One embodiment comprises adjusting a graphical user interface in response to a tilt of a device. In this way, a graphical user interface may display a parallax effect in response to the device tilt.

Abstract: A programmable effects system for graphical user interfaces is disclosed. One embodiment comprises adjusting a graphical user interface in response to a tilt of a device. In this way, a graphical user interface may have viewable content not shown in a first view, where the viewable content may be displayed in a tilted view in response to the device tilt.

Abstract: A programmable effects system for graphical user interfaces is disclosed. One embodiment comprises adjusting a graphical user interface in response to a tilt of a device. In this way, a graphical user interface may have viewable content not shown in a first view, where the viewable content may be displayed in a tilted view in response to the device tilt.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

Abstract: The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.

Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

Abstract: The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.