Abstract: A ballast having a microprocessor embedded therein is controlled via four inputs. The ballast includes a high-voltage phase-controlled signal provided by a dimmer and an infrared (IR) receiver through which the ballast can receive data signals from an IR transmitter. The ballast can also receive commands from other ballasts or a master control on the serial digital communication link, such as a DALI protocol link. The fourth input is an analog signal, which is simply a DC signal that linearly ranges in value from a predetermined lower limit to a predetermined upper limit, corresponding to the 0% to 100% dimming range of the load. The output stage of the ballast includes one or more FETs, which are used to control the current flow to the lamp. Based on these inputs, the microprocessor makes a decision on the intensity levels of the load and directly drives the FETs in the output stage.

Abstract: A ballast having a microprocessor embedded therein is controlled via four inputs. The ballast includes a high-voltage phase-controlled signal provided by a dimmer and an infrared (IR) receiver through which the ballast can receive data signals from an IR transmitter. The ballast can also receive commands from other ballasts or a master control on the serial digital communication link, such as a DALI protocol link. The fourth input is an analog signal, which is simply a DC signal that linearly ranges in value from a predetermined lower limit to a predetermined upper limit, corresponding to the 0% to 100% dimming range of the load. The output stage of the ballast includes one or more FETs, which are used to control the current flow to the lamp. Based on these inputs, the microprocessor makes a decision on the intensity levels of the load and directly drives the FETs in the output stage.

Abstract: A ballast having a microprocessor embedded therein is controlled via four inputs. The ballast includes a high-voltage phase-controlled signal provided by a dimmer and an infrared (IR) receiver through which the ballast can receive data signals from an IR transmitter. The ballast can also receive commands from other ballasts or a master control on the serial digital communication link, such as a DALI protocol link. The fourth input is an analog signal, which is simply a DC signal that linearly ranges in value from a predetermined lower limit to a predetermined upper limit, corresponding to the 0% to 100% dimming range of the load. The output stage of the ballast includes one or more FETs, which are used to control the current flow to the lamp. Based on these inputs, the microprocessor makes a decision on the intensity levels of the load and directly drives the FETs in the output stage.

Abstract: A ballast having a microprocessor embedded therein is controlled via four inputs. The ballast includes a high-voltage phase-controlled signal provided by a dimmer and an infrared (IR) receiver through which the ballast can receive data signals from an IR transmitter. The ballast can also receive commands from other ballasts or a master control on the serial digital communication link, such as a DALI protocol link. The fourth input is an analog signal, which is simply a DC signal that linearly ranges in value from a predetermined lower limit to a predetermined upper limit, corresponding to the 0% to 100% dimming range of the load. The output stage of the ballast includes one or more FETs, which are used to control the current flow to the lamp. Based on these inputs, the microprocessor makes a decision on the intensity levels of the load and directly drives the FETs in the output stage.

Abstract: A digital processing system includes first and second processors and first and second random access memories (RAMs) respectively associated with the first and second processors. Each of the first and second RAMs includes a plurality of independent memory cells, each cell in the first RAM having associated therewith a corresponding cell in the second RAM. Input/output circuitry provides independent access by the first processor to the first RAM and by the second processor to the second RAM. Control logic is responsive to a transfer control signal to simultaneously transfer data stored in the memory cells of one of the first and second RAMs into the corresponding cells of the other of the first and second RAMs. Data may be selectively transferred such that only data stored in selected memory cells is transferred between the first and second RAMs.

Abstract: Memory apparatus for simultaneously transferring data between corresponding memory cells of two RAMs is disclosed. The two memories are fabricated on a common integrated circuit chip substrate with the corresponding memory cells of the two memories positioned adjacent one another and interconnected through a pair of transfer transistors. The transfer transistors as well as the power supply to each memory cell are controllable to cause the simultaneous copying of the data from the cells of one RAM into the corresponding cells of the other RAM.

Abstract: Memory apparatus for simultaneously transferring data between corresponding memory cells of two RAMs is disclosed. The two memories are fabricated on a common integrated circuit chip substrate with the corresponding memory cells of the two memories positioned adjacent one another and interconnected through a pair of transfer transistors. The transfer transistors as well as the power supply to each memory cell are controllable to cause the simultaneous copying of the data from the cells of one RAM into the corresponding cells of the other RAM.

Abstract: A dual inverter circuit wherein the first inverter circuit includes a pair of phase splitter transistors, one serving to feed the base of the pull-up transistor in the first inverter circuit and the other serving to feed the base of the phase splitter transistor in the second inverter circuit. The circuit provides a minimum delay time between the operation of the first inverter and the turn-on time of the second inverter while also providing active pull-up circuits, i.e., pull-up transistors, in the two inverters to insure fast operate times for both inverters especially desirable when feeding into large capacitance loads.