Patents by Inventor Robert A. Ashton
Robert A. Ashton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9316673Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.Type: GrantFiled: July 2, 2014Date of Patent: April 19, 2016Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Robert A. Ashton
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Publication number: 20140312922Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.Type: ApplicationFiled: July 2, 2014Publication date: October 23, 2014Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Robert A. ASHTON
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Patent number: 8803529Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.Type: GrantFiled: September 17, 2013Date of Patent: August 12, 2014Assignee: Semiconductor Components Industries, LLCInventor: Robert A. Ashton
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Publication number: 20140009177Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.Type: ApplicationFiled: September 17, 2013Publication date: January 9, 2014Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Robert A. Ashton
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Patent number: 8564301Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.Type: GrantFiled: November 8, 2010Date of Patent: October 22, 2013Assignee: Semiconductor Components Industries, LLCInventor: Robert A. Ashton
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Publication number: 20120112774Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.Type: ApplicationFiled: November 8, 2010Publication date: May 10, 2012Inventor: Robert A. Ashton
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Patent number: 6555910Abstract: The present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therein, or depending on the device, therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.Type: GrantFiled: August 29, 2000Date of Patent: April 29, 2003Assignee: Agere Systems Inc.Inventors: Robert A. Ashton, Steven A. Lytle, Mary D. Roby, Morgan J. Thoma, Daniel J. Vitkavage
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Patent number: 6534834Abstract: A snapback device functions as a semiconductor protection circuit to prevent damage to integrated circuits due to events such as electrostatic discharge and the like. The snapback device is capable of carrying considerable current at a reduced voltage once it snaps back into bipolar operation mode after its trigger point is achieved. The snapback device includes the advantage of a low breakdown voltage which enables the snapback device to snap back into bipolar mode before damage is done to active circuit components due to their breakdown voltages being exceeded. The snapback device includes n+ active areas formed within a p-well substrate region and each active area includes a polysilicon film overlapping the active area but insulated therefrom by a dielectric film. Each n+ active area and polysilicon film are coupled by a conductive film and the components combine to form one electric node.Type: GrantFiled: December 19, 2001Date of Patent: March 18, 2003Assignee: Agere Systems, Inc.Inventors: Robert A. Ashton, Yehuda Smooha
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Patent number: 6144040Abstract: The present invention provides a van der Pauw semiconductor test structure for and a method of testing a resistivity of a doped area formed within a substrate of a semiconductor wafer which may be under a diffusion area or a gate structure. The test structure can include field oxide regions formed on a surface of the substrate and a base doped substrate formed within the substrate. Further, the test structure includes a first primary tub and secondary tubs that are formed within the base doped substrate, each of the secondary tubs having a first diffusion region formed adjacent to an inner isolation structure and a second diffusion region formed adjacent to an outer isolation structure. A second primary tub is located adjacent the first primary tub and a dielectric layer is formed over the substrate having contacts formed within the dielectric layer and between the isolation structures.Type: GrantFiled: January 22, 1999Date of Patent: November 7, 2000Assignee: Lucent Technologies Inc.Inventor: Robert A. Ashton