Patents by Inventor Robert A. Ashton

Robert A. Ashton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9316673
    Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: April 19, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Robert A. Ashton
  • Publication number: 20140312922
    Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.
    Type: Application
    Filed: July 2, 2014
    Publication date: October 23, 2014
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Robert A. ASHTON
  • Patent number: 8803529
    Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Robert A. Ashton
  • Publication number: 20140009177
    Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.
    Type: Application
    Filed: September 17, 2013
    Publication date: January 9, 2014
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Robert A. Ashton
  • Patent number: 8564301
    Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: October 22, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Robert A. Ashton
  • Publication number: 20120112774
    Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.
    Type: Application
    Filed: November 8, 2010
    Publication date: May 10, 2012
    Inventor: Robert A. Ashton
  • Patent number: 6555910
    Abstract: The present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therein, or depending on the device, therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: April 29, 2003
    Assignee: Agere Systems Inc.
    Inventors: Robert A. Ashton, Steven A. Lytle, Mary D. Roby, Morgan J. Thoma, Daniel J. Vitkavage
  • Patent number: 6534834
    Abstract: A snapback device functions as a semiconductor protection circuit to prevent damage to integrated circuits due to events such as electrostatic discharge and the like. The snapback device is capable of carrying considerable current at a reduced voltage once it snaps back into bipolar operation mode after its trigger point is achieved. The snapback device includes the advantage of a low breakdown voltage which enables the snapback device to snap back into bipolar mode before damage is done to active circuit components due to their breakdown voltages being exceeded. The snapback device includes n+ active areas formed within a p-well substrate region and each active area includes a polysilicon film overlapping the active area but insulated therefrom by a dielectric film. Each n+ active area and polysilicon film are coupled by a conductive film and the components combine to form one electric node.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: March 18, 2003
    Assignee: Agere Systems, Inc.
    Inventors: Robert A. Ashton, Yehuda Smooha
  • Patent number: 6144040
    Abstract: The present invention provides a van der Pauw semiconductor test structure for and a method of testing a resistivity of a doped area formed within a substrate of a semiconductor wafer which may be under a diffusion area or a gate structure. The test structure can include field oxide regions formed on a surface of the substrate and a base doped substrate formed within the substrate. Further, the test structure includes a first primary tub and secondary tubs that are formed within the base doped substrate, each of the secondary tubs having a first diffusion region formed adjacent to an inner isolation structure and a second diffusion region formed adjacent to an outer isolation structure. A second primary tub is located adjacent the first primary tub and a dielectric layer is formed over the substrate having contacts formed within the dielectric layer and between the isolation structures.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: November 7, 2000
    Assignee: Lucent Technologies Inc.
    Inventor: Robert A. Ashton