Abstract: Systems, apparatuses, and methods related to transferring data to a memory device based on importance are described. A memory apparatus includes a first memory device, a second memory device having a lower write latency than the first memory device, and a controller coupled to the first memory device and second memory device via a compute express link (CXL) interface. The controller is configured to assign an importance level to a write request based on data associated with the write request, a hierarchy of importance levels for different data types, and the second memory device having a lower write latency than the first memory device. The controller is further configured to transfer the data to the first memory device in response to the assigned importance level having a first value and transfer the data to the second memory device in response to the assigned importance level having a second value.

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: A programmable logic device has buffers that may be selectively programmed for Schmitt-triggered and threshold-triggered operation. The programmable Schmitt-triggered buffers are connected to circuit nodes that are sensitive to noisy environments. The programmable threshold-triggered buffers are connected to circuit nodes that have critical timing requirements.

Abstract: A method for making a cutting tool such as a tap, reamer or the like, in which the entire surface of a soft high speed steel blank is coated with a formation of titanium nitride, heat treated, and then finish ground by conventional means to define the cutting edges.