Abstract: A Cloud Service Provider reconfigures a memory subsystem during routine operation, while minimizing the amount of time a server is not online. Server downtime is reduced by offloading reconfiguration of system memory to the operating system with platform assistance. The operating system enumerates potential memory configurations of the memory subsystem with associated performance characteristics in an abstracted manner and performs reconfiguration of the memory subsystem without a cold reset. When reconfiguration of the memory subsystem is deemed necessary by the operating system, the operating system examines the enumerated memory subsystem configurations provided by system firmware. After selecting the memory subsystem configuration, the operating system initiates a reconfiguration process.

Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Abstract: Methods and apparatus for mapping memory allocation to DRAM dies of a stacked memory modules are described herein. Memory address ranges in a module employing 3DS (three dimensional stacked) DRAMs (Dynamic Random Access Memories) comprising stacked DRAM dies are mapped to DRAM dies in the module based on a layer of the DRAM dies, where dies in different layers have different thermal dissipation characteristic. Chunks of the memory address range are allocated to software entities such as virtual machines (VMs) and/or applications based on a memory access rate of the VMs/applications and the thermal dissipation characteristics of the DRAM die layers, wherein VMs/applications with higher memory access rate are allocated memory on DRAM dies with higher thermal dissipation. In one aspect, memory ranks are associated with respective die layers. In response to detection of change in access rates, memory may be migrated between ranks. Interleaving at multiple levels is also supported.

Abstract: An apparatus comprising a first memory interface of a first type to couple to at least one first memory device; a second memory interface of a second type to couple to at least one second memory device; and circuitry to interleave memory requests targeting contiguous memory addresses among the at least one first memory device and the at least one second memory device.

Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Abstract: The present disclosure relates to attempting to maintain and/or repair the embedded software components of a computer and, more specifically, to attempting to maintain and/or repair the embedded software components of a server utilizing a service processor.

Abstract: System(s) and method(s) for analysis and design of genome sequences are provided. A graph representation of a genome sequence facilitates generation of a thermodynamic based quantity, e.g., an entropy-based and enthalpy-based thermodynamic tolerance [?], which in turn affords estimation of a gene sequence potential function that depends at least upon structural and functional properties of the gene sequence. The gene sequence potential (?) is determined, at least in part, via a generalized Schrödinger equation for the thermodynamic tolerance. Gene sequence potential and thermodynamic tolerance [?], and derived quantities, like thermodynamic tolerance profile and generalized homology, provide an analytic instrument for characterization of natural and synthetic gene sequences, and in conjunction with graph-based algorithms embodies a tool for design of genome sequences with predetermined properties.

Abstract: The invention provides a method for assessing drug metabolizing enzyme expression levels in whole blood. The invention enables prediction of the effectiveness or safety of a drug therapy by providing a measure of the drug metabolizing capability of the patient. The invention provides a method for detecting and quantifying CYP2D6 mRNA in biological samples, a multiplex assay for detecting SNPs of CYP2D6 gene, and a multiplex assay for detecting SNPs of NAT1 and NAT2.

Abstract: A method of chaining interrupt service routines comprises creating a chain handler module and replacing an instruction in an existing interrupt service routine with a branch directed to the chain handler module.

Abstract: A method for tracking agents across loss of state events is described. After determining the number of terminal agents within a hierarchical agent system, an algorithm forms a first matrix containing data identifying agents within the hierarchical agent system. After a potential loss of state event has occurred, the algorithm forms a second matrix containing data identifying agents within the hierarchical agent system and compares the first matrix to the second matrix. If the matrices are identical, no agent switch occurred during the potential loss of state event. If the matrices are not identical, at least one agent switch occurred during the potential loss of state event.