Abstract: A method of making an optical fiber preform includes depositing silica glass on the inside of a tube substrate via a plasma chemical vapor deposition (PCVD) operation. The parameters of the PCVD operation are controlled such that the silica glass deposited on the interior of the tube substrate contains a non-periodic array of voids in a cladding region of the optical fiber preform. The optical fiber preform may be used to produce an optical fiber having a core and a void containing cladding. The core of the optical fiber has a first index of refraction and the cladding has a second index of refraction less than that of the core.

Abstract: A method of making an optical fiber preform includes depositing silica glass soot on the inside of a substrate tube via a chemical vapor deposition operation. The silica glass soot is consolidated into silica glass under controlled conditions such that the consolidated silica glass on the interior of the substrate tube contains a non-periodic array of gaseous voids in a cladding region of the optical fiber preform. The optical fiber preform may be used to produce an optical fiber having a core and a cladding containing voids formed from the gaseous voids of the cladding region of the optical fiber preform. The core of the optical fiber has a first index of refraction and the cladding has a second index of refraction less than that of the core.

Abstract: Method of making a microstructured optical fiber. Silica glass based soot is deposited on a substrate to form at least a portion of an optical fiber preform by traversing a soot deposition burner with respect to said substrate at a burner traverse rate greater than 3 cm/sec, thereby depositing a layer of soot having a thickness less than 20 microns for each of a plurality of burner passes. At least a portion of the soot preform is then consolidated inside a furnace to remove greater than 50 percent of the air trapped in said soot preform, said consolidating taking place in a gaseous atmosphere containing krypton, nitrogen, or mixtures thereof under conditions which are effective to trap a portion of said gaseous atmosphere in said preform during said consolidation step, thereby forming a consolidated preform which when viewed in cross section will exhibit at least 50 voids therein.

Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: A system and method for extracting data from a protected region of memory loads at least a first part of extraction code into physical memory and, thereafter, activates a memory mapping facility that maps a real memory onto the physical memory and prevents programs from accessing a protected memory region of the physical memory. At least a second part of the extraction code is then loaded into the virtual memory utilizing the memory mapping facility. The extraction code is then executed to deactivate the memory mapping facility and to copy data from the protected memory region to a second physical memory region, such that reactivating the memory mapping facility will cause a real memory region to be mapped onto the second physical memory region.

Abstract: In a cache memory system, a mechanism enabling two logical cache lines to coexist within the same physical cache line, during line fill and replacement, thus minimizing the likelihood of stalling accesses to the cache while the line is being filled or replaced. A control mechanism governs access to the cache line and tracks which sub-cache line units contain old or new data, or are empty during the fill/replacement procedure. The control mechanism thus maintains a sub-cache line state for the purpose of permitting a processor to gain access to a portion of the cache line before it is completely filled or replaced.

Abstract: A point to point connection architecture for a computer I/O subsystem, resulting in a scalable tree structure. A Master I/O Concentrator (MIOC) is connected to the host bus and handles conversion between a bus oriented structure and the tree structure of the I/O subsystem. Ports away from the host bus are downstream ports and conform to a simple byte wide message protocol. Various IOCs and devices can be attached to one of the downstream ports on the MIOC. The MIOC directs transmissions to the appropriate channel based on a geographical addressing scheme. The IOC connections act as further points of branching. Ultimately IOD or I/O devices are reached, having an upstream port for connection to the IOC and a downstream port and internal logic appropriate for the particular peripheral device. Various registers are present in the IOCs and the IODs to allow determination of the topology and particular devices present. Messages and commands are transferred in the I/O subsystem in defined packets.

Abstract: A security token, such as a bank note or identity card, comprises a sheet-like substrate made up from film of transparent bi-axially oriented polymer coated with layers of opaque and heat activated adhesive material. The opaque layer is applied in such a way as to leave a transparent area for inspection of a security device, for example, a diffraction grating, incorporated in the polymer film. The substrate may bear printed or other identifying indicia and is protected with an intimately bonded layer of transparent polymeric material.