Patents by Inventor Robert A. Briano

Robert A. Briano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973008
    Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 30, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Shixi Louis Liu, William P. Taylor
  • Publication number: 20240044946
    Abstract: A sensor package comprising a lead frame, a current sensor die, and an interposer. The lead frame includes: (i) a primary conductor, (ii) a plurality of secondary leads, and (iii) a layer of dielectric material that is disposed between the primary conductor and the plurality of secondary leads. The current sensor die includes one or more sensing elements. The current sensor die is configured to measure a level of electrical current through the primary conductor of the lead frame. The interposer is disposed over the layer of dielectric material. The interposer includes a plurality of conductive traces that are configured to couple each of a plurality of terminals of the current sensor die to a respective one of the plurality of secondary leads.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Michael C. Doogue, William P. Taylor
  • Publication number: 20240047314
    Abstract: A current sensor integrated circuit package includes a primary conductor having an input portion and an output portion, both with reduced area edges. Secondary leads each have an exposed portion and an elongated portion that is offset with respect to the exposed portion. A semiconductor die is disposed adjacent to the primary conductor on an insulator portion and at least one magnetic field sensing element is supported by the semiconductor die. A package body includes a first portion enclosing the semiconductor die and a portion of the primary conductor and a second portion enclosing the elongated portion of the plurality of secondary leads. The first package body portion has a first width configured to expose the input and output portions of the primary conductor and the second package body portion has a second width between a first and second package body side edges that is larger than the first width.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 8, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Shixi Louis Liu
  • Patent number: 11768229
    Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by a magnetic sensing element supported by a semiconductor die adjacent to the primary conductor. The primary current path contains a mechanical locking feature. The thickness of the molded body of the package is reduced to improve vibration immunity.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: September 26, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventors: Bradley Boden, Rishikesh Nikam, Robert A. Briano
  • Patent number: 11721648
    Abstract: Methods and apparatus for a signal isolator having reduced parasitics. An example embodiment, a signal isolator and include a first metal region electrically connected to a first die portion, a second die portion isolated from the first die portion, and a second metal region electrically connected to the second die portion. A third metal region can be electrically isolated from the first and second metal regions and a third die portion can be electrically isolated from the first, second and third metal regions. In embodiments, the first metal region, the second metal region, and the third metal region provide a first isolated signal path from the first die portion to the second die portion.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: August 8, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Alejandro Gabriel Milesi
  • Publication number: 20230060219
    Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by one or more magnetic sensing elements supported by a semiconductor die adjacent to the primary conductor. A method of fabricating the packaged current sensor integrated circuit includes partially encasing the lead frame in a first mold material, applying an insulator to one or more die attach pads, attaching a die to the insulator, electrically connecting the die to secondary leads, and providing a second mold to the subassembly. The package is configured to provide increased voltage isolation.
    Type: Application
    Filed: November 8, 2022
    Publication date: March 2, 2023
    Applicant: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Robert A. Briano, Natasha Healey
  • Publication number: 20230058695
    Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by a magnetic sensing element supported by a semiconductor die adjacent to the primary conductor. The primary current path contains a mechanical locking feature. The thickness of the molded body of the package is reduced to improve vibration immunity.
    Type: Application
    Filed: March 10, 2022
    Publication date: February 23, 2023
    Applicant: Allegro MicroSystems, LLC
    Inventors: Bradley Boden, Rishikesh Nikam, Robert A. Briano
  • Patent number: 11561112
    Abstract: Methods and apparatus for a current sensor having an elongate current conductor having an input and an output and a longitudinal axis. First, second, third and fourth magnetic field sensing elements are coupled in a bridge configuration and positioned in a plane parallel to a surface of the current conductor such that the second and fourth magnetic field sensing elements comprise inner elements and the first and third magnetic field sensing elements comprise outer elements. Embodiments of the sensor reduce the effects of stray fields on the sensor.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 24, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Paul A. David
  • Patent number: 11519946
    Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by a magnetic sensing element supported by a semiconductor die adjacent to the primary conductor. Each of the input portion and output portion of the primary conductor is exposed from orthogonal sides of the package body. A fault signal may be provided to indicate an overcurrent condition in the integrated current sensor package. The primary current path may be made of a thick lead frame material to reduce the primary current path resistance.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: December 6, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventors: Simon E. Rock, Alexander Latham, Robert A. Briano, Shixi Louis Liu
  • Publication number: 20220238461
    Abstract: Methods and apparatus for a signal isolator having reduced parasitics. An example embodiment, a signal isolator and include a first metal region electrically connected to a first die portion, a second die portion isolated from the first die portion, and a second metal region electrically connected to the second die portion. A third metal region can be electrically isolated from the first and second metal regions and a third die portion can be electrically isolated from the first, second and third metal regions. In embodiments, the first metal region, the second metal region, and the third metal region provide a first isolated signal path from the first die portion to the second die portion.
    Type: Application
    Filed: April 19, 2022
    Publication date: July 28, 2022
    Applicant: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Alejandro Gabriel Milesi
  • Publication number: 20220165647
    Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Applicant: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Shixi Louis Liu, William P. Taylor
  • Patent number: 11342288
    Abstract: Methods and apparatus for a signal isolator having reduced parasitics. An example embodiment, a signal isolator and include a first metal region electrically connected to a first die portion, a second die portion isolated from the first die portion, and a second metal region electrically connected to the second die portion. A third metal region can be electrically isolated from the first and second metal regions and a third die portion can be electrically isolated from the first, second and third metal regions. In embodiments, the first metal region, the second metal region, and the third metal region provide a first isolated signal path from the first die portion to the second die portion.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: May 24, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Alejandro Gabriel Milesi
  • Publication number: 20220137103
    Abstract: Methods and apparatus for measuring a current difference between at least two current traces in a circuit board. Each wire or trace generates a magnetic field which may then be measured by at least one magnetic field sensing element positioned on an integrated circuit, such as a current sensor integrated circuit or a differential magnetic field sensor integrated circuit. An output disconnect signal may be provided from the current sensor or differential magnetic field sensing integrated circuit to indicate that a current difference above a predetermined threshold exists in the two or more current traces.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Applicant: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Wade Bussing, Timothy A. Clark
  • Patent number: 11320466
    Abstract: Methods and apparatus for measuring a current difference between at least two current traces in a circuit board. Each wire or trace generates a magnetic field which may then be measured by at least one magnetic field sensing element positioned on an integrated circuit, such as a current sensor integrated circuit or a differential magnetic field sensor integrated circuit. An output disconnect signal may be provided from the current sensor or differential magnetic field sensing integrated circuit to indicate that a current difference above a predetermined threshold exists in the two or more current traces.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: May 3, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Wade Bussing, Timothy A. Clark
  • Patent number: 11289406
    Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 29, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Shixi Louis Liu, William P. Taylor
  • Publication number: 20210285794
    Abstract: Methods and apparatus for a current sensor having an elongate current conductor having an input and an output and a longitudinal axis. First, second, third and fourth magnetic field sensing elements are coupled in a bridge configuration and positioned in a plane parallel to a surface of the current conductor such that the second and fourth magnetic field sensing elements comprise inner elements and the first and third magnetic field sensing elements comprise outer elements. Embodiments of the sensor reduce the effects of stray fields on the sensor.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Applicant: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Paul A. David
  • Patent number: 11112465
    Abstract: Methods and apparatus for monitoring the integrity of an insulative material. A monitoring module detects a leakage current corresponding to an injection signal into the insulative material by a signal source. An output can provide an insulation fault signal when the leakage current is greater than a given threshold.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 7, 2021
    Assignee: Allegro Microsystems, LLC
    Inventor: Robert A. Briano
  • Patent number: 11115244
    Abstract: A signal isolator integrated circuit package includes a first circuit having a first input and a first output, a second circuit having a second input and a second output, an isolation barrier layer between the first circuit and the second circuit, wherein the second output of the second circuit is coupled to the first input of the first circuit through the isolation barrier. The signal isolator includes a comparator configured to compare the first input of the first circuit to the second output of the second circuit. The second output can be configured to convey at least three states, including a first state indicative of a logical high of an input signal received at the first input, a second state indicative of a logical low of the input signal, and a third state indicative of a fault condition.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 7, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Pedram Sotoodeh Shahnani, Cory Voisine
  • Patent number: 11029366
    Abstract: Methods and apparatus for an IC package having an impedance detector module configured to have: a first connection to a first external energy source via a first IO pin of the IC package and a second connection to a detection component. In embodiments, the detection component is configured for connection to a first ground for the first external energy source via a second IO pin of the IC package, and to a barrier component, which is configured for connection to a second ground for a second external energy source via a third IO pin of the IC package. The impedance detector module is configured to detect a disconnection or degradation of a connection to ground.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: June 8, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventor: Robert A. Briano
  • Publication number: 20210082789
    Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Shixi Louis Liu, William P. Taylor