Abstract: DMA transfer of audio and video data. The audio and video data may be received over a serial bus. A DMA engine may provide audio and video data packets to data storage logic based on the audio and video data. The DMA engine may provide each of the audio data packets with a first, same destination address of a first memory and may provide each of the video data packets with a second, same destination address of the first memory. The data storage logic may maintain first and second pointers that indicate a next current memory location for audio data in a first buffer and video data in a second buffer in the first memory, respectively. The data storage logic may receive and store the audio and video data packets at respective locations in the first and second buffers based on current values of the first and second pointers.

Abstract: DMA transfer of audio and video data. The audio and video data may be received over a serial bus. A DMA engine may provide audio and video data packets to data storage logic based on the audio and video data. The DMA engine may provide each of the audio data packets with a first, same destination address of a first memory and may provide each of the video data packets with a second, same destination address of the first memory. The data storage logic may maintain first and second pointers that indicate a next current memory location for audio data in a first buffer and video data in a second buffer in the first memory, respectively. The data storage logic may receive and store the audio and video data packets at respective locations in the first and second buffers based on current values of the first and second pointers.

Abstract: A processor includes controller circuitry configurable to determine for a given packet or other protocol data unit (PDU) received by the processor whether the given PDU is a single-cell PDU. If the given PDU is a single-cell PDU, information characterizing the given PDU is stored in first memory circuitry internal to the processor, without utilizing a linked list data structure. If the given PDU is not a single-cell PDU, information characterizing the PDU is stored in second memory circuitry external to the processor, utilizing a linked list data structure. The processor may be configured as a network processor integrated circuit to provide an interface between a network and a switch fabric in a router or switch.

Abstract: A processor includes controller circuitry operative to control the performance of a continuity check for each of a plurality of flows of protocol data units (PDUs) received by the processor. The controller circuitry is further operative to control access to a set of continuity check counters comprising a counter for each of the plurality of flows. The processor stores an identifier for each of a subset of the plurality of flows in a continuity check cache, and determines if a given flow for which a PDU is received in the processor has a corresponding entry in the continuity check cache. If the given flow has such an entry, the processor prevents a corresponding one of the continuity check counters from being updated, and if the given flow does not have such an entry, the processor clears the corresponding one of the continuity check counters and stores a flow identifier for the given flow in the continuity check cache.

Abstract: A processor includes controller circuitry operative to control performance monitoring for at least one flow of cells or other protocol data units received by the processor. The controller circuitry includes a classifier and is operative to access memory circuitry associated with the processor. The classifier is configured to perform at least a first pass classification of at least a subset of the protocol data units. The controller circuitry in conjunction with a first pass classification of a protocol data unit of a first type is operative to execute a first script, and in conjunction with a first pass classification of a protocol data unit of a second type is operative to execute a second script different than the first script. A result of execution of at least one of the first and second scripts is stored in the memory circuitry.