Patents by Inventor Robert A. Gasser

Robert A. Gasser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Guard wall to reduce delamination effects within a semiconductor die
    Patent number: 5986315
    Abstract: A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: November 16, 1999
    Assignee: Intel Corporation
    Inventors: Melton C. Bost, Robert A. Gasser, Shi-Ning Yang, Timothy L. Deeter
  • Single poly devices for monitoring the level and polarity of process induced charging in a MOS process
    Patent number: 5844300
    Abstract: A monitoring device to monitor process induced charge employing a single layer of polysilicon forming a floating gate. The device comprises two capacitors, one for charging and the other for discharging a floating gate of an n-channel transistor. Embodiments which permit the monitoring of positive charge, negative charge and both positive and negative charge are described. The device is reusable and lends itself to in-line monitoring as opposed to some prior art devices used for end-of-line monitoring.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: December 1, 1998
    Assignee: Intel Corporation
    Inventors: Mohsen Alavi, Payman Aminzadeh, Robert A. Gasser, Sunit Tyagi, Gilroy J. Vandentop
  • Method of forming a guard wall to reduce delamination effects
    Patent number: 5270256
    Abstract: A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: December 14, 1993
    Assignee: Intel Corporation
    Inventors: Melton C. Bost, Robert A. Gasser, Shi-Ning Yang, Timothy L. Deeter