Patents by Inventor Robert A. Heaton
Robert A. Heaton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935857Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).Type: GrantFiled: September 23, 2022Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Kristof Darmawaikarta, Robert May, Sashi Kandanur, Sri Ranga Sai Boyapati, Srinivas Pietambaram, Steve Cho, Jung Kyu Han, Thomas Heaton, Ali Lehaf, Ravindranadh Eluri, Hiroki Tanaka, Aleksandar Aleksov, Dilan Seneviratne
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Patent number: 11829241Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.Type: GrantFiled: June 14, 2022Date of Patent: November 28, 2023Assignee: Cadence Design Systems, Inc.Inventors: Angus William McLaren, Robert A. Heaton, Aaron Ali, Frederick A. Ware
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Publication number: 20220374306Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.Type: ApplicationFiled: June 14, 2022Publication date: November 24, 2022Inventors: Angus William McLAREN, Robert A. HEATON, Aaron ALI, Frederick A. WARE
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Patent number: 11392452Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.Type: GrantFiled: June 14, 2019Date of Patent: July 19, 2022Assignee: Rambus, Inc.Inventors: Angus William McLaren, Robert A. Heaton, Aaron Ali, Frederick A. Ware
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Publication number: 20210248031Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.Type: ApplicationFiled: June 14, 2019Publication date: August 12, 2021Inventors: Angus William McLAREN, Robert A. HEATON, Aaron ALI, Frederick A. WARE
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Patent number: 7969186Abstract: A mixed signal integrated circuit includes a digital logic array and an analog cell array. Each cell of the analog cell array shares a common architecture and is fully programmable. An analog cell includes mirror NFETs, cascode NFETs, differential pair NFETs, differential pair PFETs, cascode PFETs and mirror PFETs. An analog cell may also include special purpose components, such as low value resistors, high value resistors and PFETs.Type: GrantFiled: June 2, 2009Date of Patent: June 28, 2011Assignee: MIPS TechnologiesInventor: Robert Heaton
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Publication number: 20100301897Abstract: A mixed signal integrated circuit includes a digital logic array and an analog cell array. Each cell of the analog cell array shares a common architecture and is fully programmable. An analog cell includes mirror NFETs, cascode NFETs, differential pair NFETs, differential pair PFETs, cascode PFETs and mirror PFETs. An analog cell may also include special purpose components, such as low value resistors, high value resistors and PFETs.Type: ApplicationFiled: June 2, 2009Publication date: December 2, 2010Inventor: Robert Heaton
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Patent number: 7706488Abstract: A synchronization pulse representing a symbol boundary in a signal such as an OFDM signal is obtained by deriving a first signal representing the difference between the amplitudes of samples separated by the useful part of an OFDM symbol, a second signal representing the phase difference between the samples, and combining the first and second signals to derive a resultant signal. The resultant signal is examined and the synchronization pulse generated in response to the signal changing in a predetermined manner.Type: GrantFiled: April 15, 2004Date of Patent: April 27, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nongji Chen, Robert Heaton, Miyuki Tanaka
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Publication number: 20040208269Abstract: A synchronisation pulse representing a symbol boundary in a signal such as an OFDM signal is obtained by deriving a first signal representing the difference between the amplitudes of samples separated by the useful part of an OFDM symbol, a second signal representing the phase difference between the samples, and combining the first and second signals to derive a resultant signal. The resultant signal is examined and the synchronisation pulse generated in response to the signal changing in a predetermined manner.Type: ApplicationFiled: April 15, 2004Publication date: October 21, 2004Inventors: Nongji Chen, Robert Heaton, Miyuki Tanaka
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Publication number: 20020084940Abstract: An array of in-phase current loops are disposed adjacent to one another to define a surface and to define a virtual current loop at a periphery of the surface that produces a same direction virtual current while current in adjacent portions of adjacent current loops flows in opposite directions, to thereby wirelessly project power from the surface. It has been found according to the invention that the array of in-phase current loops that are disposed adjacent to one another to define a surface and to define a virtual current loop at a periphery of the surface that produces a same direction virtual current while current in adjacent portions of adjacent current loops flows in opposite directions, can provide acceptable power to RFID tags, while reducing the risk of violating regulatory constraints. A plurality of arrays of in-phase current loops also may be provided. The multiple arrays of in-phase current loops are disposed adjacent to one another to define a surface.Type: ApplicationFiled: November 8, 2001Publication date: July 4, 2002Inventors: Wayne D. Dettloff, William E. Batchelor, Robert A. Heaton, Michael B. Steer
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Patent number: 6388628Abstract: An array of in-phase current loops are disposed adjacent to one another to define a surface and to define a virtual current loop at a periphery of the surface that produces a same direction virtual current while current in adjacent portions of adjacent current loops flows in opposite directions, to thereby wirelessly project power from the surface. It has been found according to the invention that the array of in-phase current loops that are disposed adjacent to one another to define a surface and to define a virtual current loop at a periphery of the surface that produces a same direction virtual current while current in adjacent portions of adjacent current loops flows in opposite directions, can provide acceptable power to RFID tags, while reducing the risk of violating regulatory constraints. A plurality of arrays of in-phase current loops also may be provided. The multiple arrays of in-phase current loops are disposed adjacent to one another to define a surface.Type: GrantFiled: May 14, 1999Date of Patent: May 14, 2002Assignee: db Tag, Inc.Inventors: Wayne D. Dettloff, William E. Batchelor, Robert A. Heaton, Michael B. Steer
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Patent number: 6125893Abstract: A container (2) for a liquid anaesthetic agent for supplying the agent to an anaesthetic vaporizer comprises a reservoir for the liquid agent, a valve (6) which, when closed, prevents the flow of the liquid agent from the reservoir, a tubular outlet (10) through which the liquid can leave the reservoir when the valve is open. An O-ring (20) at the free end of the conduit provides a sealing surface for forming a seal with a corresponding sealing surface provided at an inlet to a vaporizer to which the anaesthetic agent is to be supplied. A flange (22) engages a guide on the vaporizer, to retain the container in contact with the vaporizer.Type: GrantFiled: March 5, 1997Date of Patent: October 3, 2000Assignee: Datex-Ohmeda, Inc.Inventors: Robert E. Braatz, Raymond S. Gregory, Robert A. Heaton, Keith Whitaker, David C. Sampson
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Patent number: 5664108Abstract: In a fast Ethernet, each station is connected to the hub by four unshielded twisted pairs. A first pair is transmit only for the station and receive only for the hub, a second pair is transmit only for the hub and receive only for the station, and the third and fourth pairs are bidirectional. Both the station and the hub use their transmit only and the bidirectional pairs for data transmission and their receive only pair for collision detection.Type: GrantFiled: April 26, 1996Date of Patent: September 2, 1997Assignee: Standard Microsystems CorporationInventors: Robert Heaton, Nariman Yousefi, Khosrow Sadeghi, David Fischer
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Patent number: 5617906Abstract: A container (2) for a liquid anaesthetic agent for supplying the agent to an anaesthetic vaporiser comprises a reservoir for the liquid agent, a valve (6) which, when closed, prevents the flow of the liquid agent from the reservoir, a tubular outlet (10) through which the liquid can leave the reservoir when the valve is open. An O-ring (20) at the free end of the conduit provides a sealing surface for forming a seal with a corresponding sealing surface provided at an inlet to a vaporiser to which the anaesthetic agent is to be supplied. A flange (22) engages a guide on the vaporiser, to retain the container in contact with the vaporiser.Type: GrantFiled: May 26, 1995Date of Patent: April 8, 1997Assignee: The BOC Group plcInventors: Robert E. Braatz, Raymond S. Gregory, Robert A. Heaton, Keith Whitaker, David C. Sampson
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Patent number: 5544323Abstract: In a fast Ethernet, each station is connected to the hub by four unshielded twisted pairs. A first pair is transmit only for the station and receive only for the hub, a second pair is transmit only for the hub and receive only for the station, and the third and fourth pairs are bidirectional. Both the station and the hub use their transmit only and the bidirectional pairs for data transmission and their receive only pair for collision detection.Type: GrantFiled: September 23, 1993Date of Patent: August 6, 1996Assignee: Standard Microsystems Corp.Inventors: Robert Heaton, Nariman Yousefi, Khosrow Sadeghi, David Fischer
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Patent number: 5381836Abstract: A system for delivery of volatile liquid drugs as supplied to a patient by an anaesthetic vaporizer comprises a supply container (2) and a vaporizer (32) which includes a sump. Each of the supply container and the vaporizer is provided with a valve assembly (6, 34) which, when closed, prevent passage of fluid from the supply container into the sump. The supply container and the sump are connected to one another by means of a bayonet connection, which is made when indexing elements on the containers correspond. The valve assemblies in the containers are opened when the containers are connected to one another by means of an insert (40) located within an inlet conduit (10) linking the two containers.The inlet conduit (10) is rotatable between lowered and raised positions, to open a valve (37) by which flow of fluid into and out of a reservoir for fluid in the sump can be controlled.Type: GrantFiled: July 23, 1993Date of Patent: January 17, 1995Assignee: The BOC Group plcInventors: Robert E. Braatz, Raymond S. Gregory, Robert A. Heaton, Keith Whitaker, David C. Sampson
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Patent number: 4919125Abstract: An anaesthetic vaporiser 1 the by-pass type includes a thermally responsive valve 52 in its second by-pass stream which valve 52 is located immediately below the sump 12 of the vaporiser. This offers the advantage that any difference in temperature between the valve 52 and liquid anaesthetic contained in the sump 12 is very small even when the liquid anaesthetic temperature is changing rapidly. Furthermore, the valve 52 is readily accessible for maintenance and calibration.Type: GrantFiled: April 24, 1989Date of Patent: April 24, 1990Assignee: BOC Group PLC.Inventors: Robert A. Heaton, Stuart C. Leach, Joseph Hancock, Neil A. Sandy
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Patent number: 4518145Abstract: A valve for controlling flow of abrasive media from a blast tank to a nozzle, utilizes rollers for constricting a straight-through tube. In this way the valve meters the flow of the abrasive media into a blast hose through which air is directed under pressure as a carrier for the media. Contact with the media within the valve is limited to a radially constrictable tube adapted for ready replacement as the only component subject to the destructive characteristics of media such as mineral grit, sand, or the like. In association with the pinch tube housing, means is provided permitting ready interchange of manual and automatic tube-constricting assemblies. In the automatic configuration, the size of the valve orifice through which the media passes can be accurately and swiftly regulated by varying the pressure on a diaphragm.Type: GrantFiled: September 28, 1982Date of Patent: May 21, 1985Assignee: Empire Abrasive Equipment CorporationInventors: Douglas Keltz, Robert Heaton