Abstract: A power supply circuit for supplying current to a MOS depletion load transistor logic circuit for use in programmers for washing machines or controllers for tumble driers. The power supply circuit comprises a depletion MOS transistor having its drain-source path connected between first and second power supply rails. The conductivity of the depletion transistor is controlled by a long tail pair amplifier which compares a reference voltage derived from a source with a voltage derived from the second supply rail using a voltage divider. The voltage divider is constructed to compensate for the effects of process variations on parameters such as threshold voltage and thereby hold the voltage divider ratio substantially constant. The voltage divider comprises two enhancement MOS transistors connected in series between the second supply rail and ground and a current source in the form of a depletion MOS transistor and an enhancement transistor connected in series between the first and second supply rails.

Abstract: A voltage clamping circuit for use in coupling line voltage signals to logic control circuitry used in domestic appliances includes a voltage dropping resistor coupled between input and output terminals. A first enhancement mode MOS transistor is coupled between a junction of the resistor and the output terminal and the V.sub.DD line. The gate of the first transistor is connected to the junction, so that when the voltage at the junction rises to a threshold voltage above V.sub.DD the first transistor is rendered conductive and clamps the positive line voltage cycle. A second enhancement mode MOS transistor is connected between the junction and the V.sub.DD line and its gate is connected to a biasing means which holds the second transistor nonconductive in response to the line voltage going negative until the junction is just above the V.sub.SS level, whereafter the second transistor turns on and clamps the input above V.sub.SS.

Abstract: A high gain linear amplifier comprises an MOS transistor amplifier stage having a load circuit which includes two depletion mode transistors connected in cascode. A compensating circuit compensates the variation of threshold voltage (V.sub.T) with back bias voltage (V.sub.SB) of the cascode load transistors by applying a voltage to the gate electrode of one of said two transistors in the opposite sense to the V.sub.T -V.sub.SB variation. The compensating voltage may be produced by connecting an enhancement mode transistor in cascode with a depletion mode transistor with the drain of the enhancement transistor connected to the source of the depletion transistor and to the common connection of their gates which also are connected to the gates of the load transistors.