Patents by Inventor Robert A. Iannucci
Robert A. Iannucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10833725Abstract: A method of providing wireless communications in a wireless network can include wirelessly receiving a chirp spread-spectrum modulated signal at a first gateway device, the chirp spread-spectrum modulated signal being transmitted by a remote client device. The chirp spread-spectrum modulated signal can be demodulated at the first gateway device to provide demodulated data at the first gateway device. The demodulated data can be processed to provide an indication that a decode of a packet including the demodulated data failed. Time adjacent chirps included in the demodulated data can be combined to provide combined data at the first gateway device. A message can be transmitted from the first gateway device to a remote server responsive to an amplitude of the combined data exceeding a threshold value and the indication that the decode of the packet including the demodulated data failed.Type: GrantFiled: June 2, 2020Date of Patent: November 10, 2020Assignee: Carnegie Mellon UniversityInventors: Adwait Dongare, Artur Balanuta, Akshay Gadre, Robert Iannucci, Swarun Kumar, Anh Luong, Revathy Narayanan, Anthony Rowe
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Publication number: 20200304169Abstract: A method of providing wireless communications in a wireless network can include wirelessly receiving a chirp spread-spectrum modulated signal at a first gateway device, the chirp spread-spectrum modulated signal being transmitted by a remote client device. The chirp spread-spectrum modulated signal can be demodulated at the first gateway device to provide demodulated data at the first gateway device. The demodulated data can be processed to provide an indication that a decode of a packet including the demodulated data failed. Time adjacent chirps included in the demodulated data can be combined to provide combined data at the first gateway device. A message can be transmitted from the first gateway device to a remote server responsive to an amplitude of the combined data exceeding a threshold value and the indication that the decode of the packet including the demodulated data failed.Type: ApplicationFiled: June 2, 2020Publication date: September 24, 2020Inventors: Adwait Dongare, Artur Balanuta, Akshay Gadre, Robert Iannucci, Swarun Kumar, Anh Luong, Revathy Narayanan, Anthony Rowe
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Patent number: 10735047Abstract: A method of providing wireless communications in a wireless network can include wirelessly receiving a chirp spread-spectrum modulated signal at a first gateway device, the chirp spread-spectrum modulated signal being transmitted by a remote client device. The chirp spread-spectrum modulated signal can be demodulated at the first gateway device to provide demodulated data at the first gateway device. The demodulated data can be processed to provide an indication that a decode of a packet including the demodulated data failed. Time adjacent chirps included in the demodulated data can be combined to provide combined data at the first gateway device. A message can be transmitted from the first gateway device to a remote server responsive to an amplitude of the combined data exceeding a threshold value and the indication that the decode of the packet including the demodulated data failed.Type: GrantFiled: April 4, 2019Date of Patent: August 4, 2020Assignee: Carnegie Mellon UniversityInventors: Adwait Dongare, Artur Balanuta, Akshay Gadre, Robert Iannucci, Swarun Kumar, Anh Luong, Revathy Narayanan, Anthony Rowe
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Publication number: 20190312610Abstract: A method of providing wireless communications in a wireless network can include wirelessly receiving a chirp spread-spectrum modulated signal at a first gateway device, the chirp spread-spectrum modulated signal being transmitted by a remote client device. The chirp spread-spectrum modulated signal can be demodulated at the first gateway device to provide demodulated data at the first gateway device. The demodulated data can be processed to provide an indication that a decode of a packet including the demodulated data failed. Time adjacent chirps included in the demodulated data can be combined to provide combined data at the first gateway device. A message can be transmitted from the first gateway device to a remote server responsive to an amplitude of the combined data exceeding a threshold value and the indication that the decode of the packet including the demodulated data failed.Type: ApplicationFiled: April 4, 2019Publication date: October 10, 2019Inventors: Adwait Dongare, Artur Balanuta, Akshay Gadre, Robert Iannucci, Swarun Kumar, Anh Luong, Revathy Narayanan, Anthony Rowe
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Publication number: 20140096018Abstract: A system includes a server connected to a network, the server having access to a processor, a data repository, and software executing from a non-transitory physical medium, the software providing for establishing a connection to a computing appliance, initiating and maintaining a data session with a user through a graphics user interface (GUI), training a facial recognition system to navigate to an online photo-enabled and to store a facial recognition pattern of at least one photo accessible therethrough, and to collect and store the associated descriptive metadata, associating a name tag from the photo metadata to the facial recognition pattern of the photo, detecting a photo uploaded into the image-based project by the user through the GUI, attempting to match the one or more photos to one or more photos processed by the fourth function, and the one or more photos that significantly match a pre-stored facial recognition pattern.Type: ApplicationFiled: February 20, 2013Publication date: April 3, 2014Applicant: INTERACTIVE MEMORIES, INC.Inventor: Robert Iannucci
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Patent number: 8572741Abstract: The disclosed embodiments provide a system that protects an application from malware on a host system. During operation, the system receives a command to commence execution of the application on the host system. In response to the command, the system causes a security scan to be performed on the host system to detect malware, wherein the malware can compromise the security of the application. The system also restricts one or more operations associated with the application until the security scan successfully completes.Type: GrantFiled: October 14, 2010Date of Patent: October 29, 2013Assignee: Moka5, Inc.Inventors: Constantine P. Sapuntzakis, Burt A. Toma, Phanindra V. R. Ganti, Robert A. Iannucci, Jr., Prakash Linga
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Publication number: 20120096550Abstract: The disclosed embodiments provide a system that protects an application from malware on a host system. During operation, the system receives a command to commence execution of the application on the host system. In response to the command, the system causes a security scan to be performed on the host system to detect malware, wherein the malware can compromise the security of the application. The system also restricts one or more operations associated with the application until the security scan successfully completes.Type: ApplicationFiled: October 14, 2010Publication date: April 19, 2012Applicant: MOKA5, INC.Inventors: Constantine P. Sapuntzakis, Burt A. Toma, Phanindra V. R. Ganti, Robert A. Iannucci, JR., Prakash Linga
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Patent number: 6219698Abstract: To maintain communications between first and second processing systems interconnected by a communications network, computer programing having first and second sets of instructions are stored at the first processing system. The computer programing is initialized at the first processing system to perform a task associated with the first set of instructions. In accordance with the second set of instructions, a first signal is automatically transmitted from the first processing system to the second processing system responsive to the initialization of the computer programming.Type: GrantFiled: December 19, 1997Date of Patent: April 17, 2001Assignee: Compaq Computer CorporationInventors: Robert A. Iannucci, Christopher M. Weikart
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Patent number: 5594671Abstract: A computer implemented method for simulating a physical process. The method includes storing in a memory a state vector for each of a number of voxels (i.e., lattice sites). Each state vector includes a plurality of integers, each of which corresponds to a particular momentum state of a number of possible momentum states at a voxel (lattice site) and represents the number of elements having the particular momentum state. Each integer has more than two possible values. The method also includes performing interaction operations on the state vectors that model interactions between elements of different momentum states and performing move operations on the state vectors that reflect movement of elements to new voxels.Type: GrantFiled: December 10, 1993Date of Patent: January 14, 1997Assignee: Exa CorporationInventors: Hudong Chen, Peter C. Churchill, Robert A. Iannucci, Kim Molvig, Gregory Papadopoulos, Stephen A. Remondi, Christopher M. Teixeira, Kenneth R. Traub
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Patent number: 5553305Abstract: A method and system for synchronizing execution by a processing element of threads within a process. Before execution of a thread commences, a determination is made as to whether all of the required resources for execution of the thread are available in a cache local to the processing element. If the resources are not available, then the resources are fetched from main storage and stored in one or more local caches before execution begins. If the resources are available, then execution of the thread may begin. During execution of the thread and, in particular, an instruction within the thread, the instruction may require data in order to successfully complete its execution. When this occurs, a determination is made as to whether the necessary data is available. If the data is available, the result of the instruction execution is stored and execution of the thread continues. However, if the data is unavailable, then the thread is deferred until the data becomes available and a new thread is processed.Type: GrantFiled: July 15, 1992Date of Patent: September 3, 1996Assignee: International Business Machines CorporationInventors: Steven L. Gregor, Robert A. Iannucci
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Patent number: 4685088Abstract: A novel memory system is disclosed which utilizes pipelining techniques to read data from a memory array and to write data to a memory array. More data may be read from the novel memory system, within a unit of time, relative to the amount of data which may be read from a conventional memory system during the unit of time. The novel memory system comprises a plurality of standard elements which include a memory array, including a plurality of rows and columns, a row decoder, a row driver, column sense amplifiers, and a column multiplexer. However, the novel memory system further includes latch circuits interposed between the row decoder and the row driver, between the row driver and the memory array, between the memory array and the column sense amplifiers, and between the column sense amplifiers and the column multiplexer. The same number of latch circuits are interposed in serial fashion between the incoming row and column address bus and the column multiplexer.Type: GrantFiled: April 15, 1985Date of Patent: August 4, 1987Assignee: International Business Machines CorporationInventor: Robert A. Iannucci
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Patent number: 4466077Abstract: A method and apparatus for the arithmetic division operation is disclosed in which a set of multiples of the divisor are stored in an associative memory in addresses which match the respective multiples. The most significant byte of the numerator is then compared to the contents of each associative entry. A flag is generated signifying that the corresponding entry is less than or equal to the most significant byte of the numerator. After the flags have been generated, the address of the last flag which is on, is selected. This provides a trial "digit out", which is used to address the true table of multiples and select a value which is subtracted from the left-digit-shifted numerator (or intermediate result). If no underflow condition results, the trial "digit out" is valid and should be stored and the next iteration started. For an underflow condition, the "digit out" is decremented and stored, the X1 multiple is added to the numerator and the next iteration is carried out.Type: GrantFiled: September 25, 1981Date of Patent: August 14, 1984Assignee: International Business Machines CorporationInventors: Robert A. Iannucci, James R. Kleinsteiber