Abstract: A system and method for operating a system including at least one active electronically scanned array (AESA) element incorporates drain voltage amplifier control (DRAVAC) to maintain the power amplifiers of the AESA elements at a constant gain compression level. A processor of the AESA system may dynamically program, monitor, or adjust each individual array element or component thereof. As the RF output power of the power amplifiers varies, constant gain compression is achieved by dynamically adjusting the RF input power and drain voltage to the power amplifiers. An AESA element may incorporate built-in self-test circuitry for detecting faults in the power supply to the power amplifiers as well as calibrating and calculating RF output power for a given input power by controlling the bias of a pass device serving as the amplifier current source.

Abstract: A chirp waveform generator for producing a chirp waveform ƒ(t)=sin (t2 modulus m) where modulus m is represented by n submoduli and/or factored submoduli m1-mn. Sequence generators generate digital sequence values representative of sequences of quadratic residues for each submoduli and/or factored submoduli m1-mn. Sine and cosine digital-to-analog converters (DACs) connected to the sequence generators receive the digital sequence values for each submoduli and/or factored submoduli m1-mn and produce sequences of corresponding analog sine and cosine signals. An analog processor including adders and multipliers connected to the DACs combines the sine and cosine signals to produce the chirp waveform. The argument (t2 modulus m) is an implemented phase argument that approximates a desired phase argument (?rt2). Programmable inputs on the sequence generators enable control over waveform parameters including starting phase, ramp rate and frequency.

Abstract: A signal multiplier is provided for use in multiplying an analog differential signal. The analog differential signal is defined by a first analog attribute and a second analog attribute. Preferably, a means is provided for generating a first current which corresponds to the first analog attribute. Additionally, a means is provided for generating a second current which corresponds to the second analog attribute. A first amplifier member is provided for receiving the first current as an input and providing as an output a multiple of the first current. Additionally, a second amplifier is provided for receiving the second current as an input and producing as an output a multiple of the second current. A tuneable multiplier member is provided for determining the multiple over a predetermined range of multiples. A means for maintaining a substantially linear response of the signal multiplier is also provided.

Abstract: High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

Abstract: An integrated biquadratic, continuous-time filter section includes a plurality of operational transconductance amplifiers (OTAs). Simutaneously changing a transconductance (GM) of each of the OTAs is provided by adjusting a differential voltage applied to a plurality of differential transistor pairs of each OTA. Each of the OTAs include a plurality of current sources and a common mode feedback circuit for controlling a common mode output voltage level. Changing the transconductance of the OTA is independent of the common mode voltage level control.

Abstract: A method and apparatus are provided for translating small voltage continuous signals into large full supply signals to generate a clock signal. At least one oscillator input signal is applied to a first amplifier stage for generating an amplified voltage output signal. A first inverter is coupled to the first amplifier stage. A second inverter is coupled to the first inverter. An AC coupling capacitor couples the amplified voltage output signal to the first inverter input, and a feedback resistor is connected between the output and input of the first inverter.

Abstract: A method and apparatus are provided for adaptive chip trim adjustment for an integrated circuit. A plurality of switching devices have an unswitched state and a switched state. The unswitched state corresponds to one binary value, and the switched state corresponds to another binary value. A first trim word is provided by sensing the switching devices. The switching devices are temporarily bypassed, and an override bit pattern is supplied to simulate any desired pattern of the switching device states. The override bit pattern is used for simulating a switched or unswitched state for each of the plurality of switching devices.

Abstract: A self-locking load structure for Random Access Memories is disclosed. The load structure remains coupled to the memory cell during read operations but automatically decouples from the memory during write operations. No separate decoded WRITE command must be sent to the load structure to couple and decouple the structure from the memory cell.

Abstract: A method for detecting voltage supply short circuits in integrated circuits and a circuit for implementing that method is disclosed. Entire rows of memory cells in an SRAM are coupled to a single sense line. The sense line to each row is activated individually. The sense lines are in turn coupled to a current sensing circuit. If a short exists on any memory cell in a given row, the current sensing circuit generates a low output, indicating a short circuit.

Abstract: The present invention provides an ECL EPROM circuit which uses a MOS memory cell. The invention includes a technique for programming the memory cell using MOS voltage levels, and also includes circuitry for reading the memory cell at ECL voltage levels. Thus, the programming and reading paths are split to give the ease of programming and the reprogrammability of MOS EPROM devices combined with the reading speed of PROM devices using ECL voltage levels. In one embodiment, two parallel paths are provided to a memory cell to enable it to separately receive reading and writing (programming) signals. The reading path employs ECL components for reading the cell, while the writing path contains MOS components for programming and verifying the cell. The memory cell itself contains a MOS memory element, an ECL pass element, and a sense element coupling the MOS memory element to the ECL pass element.

Abstract: A bipolar recovery circuit for a static random access memory cell is described. The circuit corrects reverse emitter-base breakdown which occurs in the known common base node writing recovery circuits. The circuit is simple, requiring little silicon chip area to fabricate. In a preferred embodiment, a separate recovery circuit is coupled to each of the true output line and the complement output line of the memory cell.

Abstract: A switching circuit for SRAM memory cells is disclosed. The circuit electronically decouples input lines to sense amplifiers from unselected arrays of memory cells. The decoupling results in a large decrease in the amount of parasitic capacitance that the selected inputs would encounter.

Abstract: A power transition circuit protects a bipolar-CMOS (BiCMOS) circuit during power transitions. Reference signals proportional to the voltage supplied to the protected circuit are monitored, and the power transition circuit determines from the voltage differential between the reference signals whether a power transition is occurring. If a transition is present, the transition circuit disables the protected BiCMOS circuit for as long as the power transition exists. An independent input signal allows the power transition circuit to disable the protected BiCMOS circuit in response to other conditions.

Abstract: A BiCMOS write-recovery method and circuit for recovering bit lines in a digital memory system provides approximately 1 nS recovery time and allows a 256K BiCMOS SRAM to achieve 10 nS access time. All bit lines in the memory system connected to a column not being read are held at a high potential, approximately equal to the upper power supply. During a write, one bit line is pulled low and its complementary bit line is clamped with a bipolar transistor to an intermediate potential, thereby preloading the complementary bit line. Following a write, the bit line that was pulled low is pulled up with a bipolar transistor to the intermediate voltage. Simultaneously, the bit line and the complementary bit line are shunted together, then returned to the high potential. Undesired bootstrap capacitance effects in the bipolar transistors are minimized by connecting a plurality of pull-up transistors in parallel, and by feeding the clamping transistors with low impedance drivers.

Abstract: A biCMOS interface circuit receives a plurality of incoming signals at a first level and supplies a plurality of output signals at a second level. The interface circuit establishes control voltages which are used to maintain an identical trip point in each of a plurality of translator circuits. Generally, the trip point is set at midway between the "high" and the "low" levels of the incoming logic signal. The control voltages assure reliable performance over a wide operating environment.

Abstract: A BiCMOS voltage reference generator circuit generates and maintains a reference voltage within 3 mV over an 80.degree. C. temperture range and over a 1 volt change in power supply level. The circuit uses feedback from the output of the reference voltage generator to the current source supplying current to the voltage reference generator. This feedback increases the effective output impedance of the current source, making the reference voltage output substantially independent of power supply variations. The circuit operates with power supply differential as low as about 3 volts, and preferably is fabricated from bipolar transistors and MOS transistors on the same chip.