Abstract: A mobile computing device includes a processor and a trigger device operatively attached to the mobile computing device and configured to generate a mechanical vibration pattern for selectively actuating the mobile computing device. A trigger interface, illustratively an accelerometer, is configured to convert the mechanical vibration pattern into an electrical signal pattern. The processor is configured to actuate a mobile computing function depending on the mechanical vibration pattern generated by the trigger device. A table of properties stored in memory correlates the mechanical vibration generated by the trigger device with a specific mobile computing function. The trigger device may include a plurality of trigger parts; and the mechanical vibration pattern generated by the trigger device may include multiple bits of data generated by the plurality of trigger parts. The mobile computing device may be in a candy bar, clam shell, or other form factor and may include a removable handle.

Abstract: A mobile computing device includes a processor and a trigger device operatively attached to the mobile computing device and configured to generate a mechanical vibration pattern for selectively actuating the mobile computing device. A trigger interface, illustratively an accelerometer, is configured to convert the mechanical vibration pattern into an electrical signal pattern. The processor is configured to actuate a mobile computing function depending on the mechanical vibration pattern generated by the trigger device. A table of properties stored in memory correlates the mechanical vibration generated by the trigger device with a specific mobile computing function. The trigger device may include a plurality of trigger parts; and the mechanical vibration pattern generated by the trigger device may include multiple bits of data generated by the plurality of trigger parts. The mobile computing device may be in a candy bar, clam shell, or other form factor and may include a removable handle.

Abstract: An externally reconfigurable input system for an electronic device is provided. The input system has the flexibility of receiving input via an input interface with the guidance of key-based substrate overlay positioned proximate a sensor array that is coupled to a printed wiring assembly. An input correlation component receives signals generated by the sensor array in response to displacement of one or more keys associated with the key-based substrate. The key-based substrate overlay is removable so as to be reconfigured.

Abstract: A system and method of detecting a barcode involves obtaining a two-dimensional source image and converting it into a frequency domain image (FDI). Frequency trends in the FDI are then analyzed to determine whether barcode information is present in the FDI. In this way, the presence, location, orientation, size and symbology of a barcode can be quickly and accurately determined.

Abstract: A reader such as a barcode reader identifies at least one potential target such as a barcode symbol in its field-of-view, and projects or transmits an indicator toward or proximate the potential target containing information about the respective potential target. Such information may include which target is currently active, the symbology in which the target is encoded, the relative position of the reader with respect to the target, the ability of the reader to decode the target, and/or ranked or sorted order information regarding the target and neighboring targets. The reader may rank, sort, prioritize or otherwise determine order based on various parameters, including symbology, position in field-of-view, size, etc., and may base such on past history of the reader and/or user, and may weight such.

Abstract: A reader such as a barcode reader identifies at least one potential target such as a barcode symbol in its field-of-view, and projects or transmits an indicator toward or proximate the potential target containing information about the respective potential target. Such information may include which target is currently active, the symbology in which the target is encoded, the relative position of the reader with respect to the target, the ability of the reader to decode the target, and/or ranked or sorted order information regarding the target and neighboring targets. The reader may rank, sort, prioritize or otherwise determine order based on various parameters, including symbology, position in field-of-view, size, etc., and may base such on past history of the reader and/or user, and may weight such.

Abstract: A system and method of detecting a barcode involves obtaining a two-dimensional source image and converting it into a frequency domain image (FDI). Frequency trends in the FDI are then analyzed to determine whether barcode information is present in the FDI. In this way, the presence, location, orientation, size and symbology of a barcode can be quickly and accurately determined.

Abstract: A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the highest priority CPU in the arbitration scheme. The arbitration circuit is combined with a controlling mechanism which interfaces to the memory device. This controller operates at a clock rate fast enough to allow the highest priority CPU to access the memory at it's highest data rate and, yet, guarantees a maximum idle period for the lower priority CPU to wait for it's interleaved memory access to complete. A single memory device provides cost and space savings. A controller is responsive to these processors to multiplex their information signals for selectively conveying information present at their address and data ports.

Abstract: An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.

Abstract: A computer system employs a process on warm boot which obviates the need to copy code in non-volatile memory to volatile memory; a normal function in a warm boot process. The computer system checks a warm boot flag which indicates that the code was previously copied on cold boot. By avoiding copying this already copied code and executing directly from the volatile memory considerable time is saved. Since BIOS code is typically on the order of 10K bytes, elimination of the necessity to rewrite BIOS and vectoring directly to BIOS image file in RAM saves on the order of ten thousand clock cycles.

Abstract: In the present invention, a single EEPROM is used to store firmware for the CPU, firmware for the SCP and the system password and other critical system data. Hardware protection is provided that prevents the CPU from accessing the portion of the EEPROM that contains the password or other critical systems data.

Abstract: The invention provides for a CPU in a digital system to control the location of the code being executed by one or more peripheral CPUs when all CPUs share a common memory. This allows the CPU to allocate convenient (e.g., unused) blocks of its address space for the code for the peripheral CPU(s). Additionally, for digital systems in which the peripheral CPU(s) cannot address the full range of the address space of the shared memory that is available to the CPU, the CPU can control the relocation of the block of code for the peripheral CPU(s) (i.e., provide a code paging system).

Abstract: The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are possible, but only under controlled conditions. Once the register has been programmed, it will no longer respond to writes.

Abstract: A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

Abstract: An enhanced parallel port interface increases the bandwidth of a standard parallel port connector while at the same time maintaining backward compatibility with a standard parallel port interface. In order to increase the data transfer rate, the software overhead is substantially reduced by hardware generated signals. As such, the desirability of using a parallel port bus expansion is greatly increased.

Abstract: An apparatus and method for tracking and interception of instructions as they are presented to the memory, selectively passing harmless data to the device and disallowing the sequences which instruct the device to perform harmful functions, such as self-erase. A software trap is provided to be transparent to the operation of the device and the host system, imposing no harmful timing delays or software overhead. Accordingly, the invention allows the use of standard electrically erasable read-only memories in an application which requires that the device be protected from global erasure. A hardware front end intercepts the software command which is used to globally erase the device.

Abstract: A method and circuit for relatively accurately measuring the die temperature of an IC, such as a microprocessor, by sensing one or more internal circuit elements which have an electrical parameter which varies as a function of temperature, such as an input protection diode. By sensing the one or more circuit elements which have an electrical parameter that is temperature dependent, the method provides a relatively more accurate measurement of the die temperature than measuring the outside temperature of the IC package. In addition, a control circuit is provided for cooling the IC during excessive temperature conditions by slowing down the clock frequency of the IC until the die temperature is within the temperature limit in order to optimize the utility of the IC during excessive temperature conditions.

Abstract: A computer disk drive control adapts the rate of data transfer between a disk drive and a CPU to correspond to one of three industry standard transfer rates. The timing of disk controller signals is provided for by a two phase state machine that receives a signal representative of a selected data transfer rate and generates disk controller signals of the appropriate frequency and configuration. Such disk controller signals cause a disk controller to effect data transfer at the selected rate. In a preferred embodiment, the two phase state machine is driven by two opposite phases of a single 24 MHz clock.

Abstract: A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

Abstract: A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.