Abstract: A primary-side power modulator for an isolated switching-mode power supply operating under secondary-side control comprising a pulse width determining circuit for real-time primary-side adjustment of a PWM control signal received from a secondary-side PWM controller. While accepting pulse width commands from an isolated secondary-side PWM controller, the pulse width determining circuit has the ability to reduce the width of the switching pulse in response to primary-side information. The power modulator may further comprise a start-up circuit for ensuring that the primary-side supply voltage is above a minimum under-voltage lock out threshold, a soft start circuit for controlling the power switch at power-up, a pulse receiver for receiving the PWM control signal generated by the secondary-side PWM controller, and a drive circuit for driving an external solid-state power switch with the adjusted PWM control signal.

Abstract: A battery charger/monitor circuit for charging and/or monitoring a plurality of series-connected cells, including a voltage sensor for sensing the voltage across each of the cells to provide a high cell voltage signal proportional to the highest voltage across any of the cells and a low cell voltage signal proportional to the lowest voltage across any of the cells. The circuit is operable in a monitor mode or a charge mode. In the monitor mode, the cells are disconnected from a load if the low cell voltage signal decreases to a first predetermined level. The circuit includes a controller which provides a control signal in response to the high cell voltage signal, the low cell voltage signal and a current sense signal, for controlling the charging of the cells.

Abstract: A battery protector for providing overvoltage and undervoltage protection to one or more series-connected cells. The battery protector includes a voltage detection and comparison circuit, providing an overvoltage signal indicative of whether the voltage across any of the cells is greater than an overvoltage threshold level and an undervoltage signal indicative of whether the voltage across any of the cells is less than an undervoltage threshold level, and a switch connected in series with the current path between the cells and a charger and/or load. In one embodiment, the switch is a four-terminal FET and a bias control circuit is provided for selectively connecting the body region of the FET to ensure that current does not flow through the parasitic FET diodes.

Abstract: A controllable bus terminator for providing a switchable termination on a bus having a plurality of conductors, wherein the controllable bus terminator includes a voltage regulator, a plurality of termination networks, each having a first terminal and a second terminal wherein the second terminal of each of the termination networks provides an output terminal of the bus terminator. The bus terminator further includes a plurality of electrically controllable switches, each of the switches having a first port coupled to the voltage regulator and a second port coupled to the first terminal of a corresponding one of the termination networks wherein each of the switches couples the corresponding termination network to the voltage regulator when the corresponding switch is in a first state and wherein each of the switches disconnects the corresponding termination network from the voltage regulator when the corresponding switch is in a second state.

Abstract: An adaptive battery charger circuit including a state machine adjusts the charging current in accordance with the battery charge acceptance. The battery charging cycle includes an initial charging phase characterized by a relatively high charge acceptance, an intermediate charging phase characterized by a decreasing charge acceptance and a rising battery temperature, and a final charging phase characterized by the battery being at substantially full charge and the charge acceptance approaching zero. Each charging phase corresponds to one or more states of the state machine. Multiple sets of conditions causing transitions between the states of operation are derived from a model of a battery under charge which relates charge acceptance, battery temperature, and cumulative supplied charge. During the intermediate charging phase, the charging current is adjusted to maintain a predetermined battery temperature for a predetermined duration.

Abstract: A switching regulator having improved dynamic response to load variations includes a load compensation circuit coupled to the output terminal. The load compensation circuit supplies current to a load coupled to the output terminal when the output voltage is less than a first predetermined level and/or diverts current away from the load when the output voltage is greater than a second predetermined level. The load compensation circuit operates in this manner until the output voltage is between the first and second predetermined levels. The load compensation circuit responds faster to load variations than the switching regulator to accommodate sudden changes in the load demand.

Abstract: A pulse width modulator voltage feedforward circuit which includes a gating circuit for providing a control signal to a charge circuit which charges an integration circuit with a current proportional to an input voltage. The integration circuit provides an output ramp signal waveform having a slope proportional to the input voltage value. The gating circuit also provide a control signal to a discharge circuit, to thus alternately charge and discharge the integration circuit. The gating circuit insures that a minimum deadtime for a transformer reset will occur regardless of input voltage variations by preventing a fixed frequency signal provided by an oscillator from beginning a new ramp waveform signal period until the integration circuit is discharged to a minimum reference voltage level.

Abstract: A high power factor regulator circuit which includes a variable multiplier, permitting the high power factor regulator circuit to be used with a number of input line voltage levels. In one embodiment a comparator determines the multiplication or gain factor to be applied in a control loop by comparing the rectified AC input voltage to a predetermined threshold value.

Abstract: A controllable bus terminator for providing a switchable termination on a bus having a plurality of conductors, wherein the controllable bus terminator includes a voltage regulator, a plurality of termination networks, each having a first terminal and a second terminal wherein the second terminal of each of the termination networks provides an output terminal of the bus terminator. The bus terminator further includes a plurality of electrically controllable switches, each of the switches having a first port coupled to the voltage regulator and a second port coupled to the first terminal of a corresponding one of the termination networks wherein each of the switches couples the corresponding termination network to the voltage regulator when the corresponding switch is in a first state and wherein each of the switches disconnects the corresponding termination network from the voltage regulator when the corresponding switch is in a second state.

Abstract: A controller for controlling a resonant switching dc to dc converter. The controller has four output terminals, each of which is capable of switching one of four transistors in a bridge power stage in such a way as to accomplish zero-voltage resonant switching. The phase relationship between the switching of the four transistors of the bridge power stage which is adjustable from approximately zero to 180.degree., results in highly-efficient, pulse-width-modulation of the output power.

Abstract: A controllable bus terminator, for providing a switchable termination on a bus having a plurality of conductors, wherein the controllable bus terminator includes a voltage regulator, a plurality of resistive networks each of the resistive networks having a first terminal and a second terminal wherein the second terminal of each of the resistive networks provides an output terminal of the bus terminator. The bus terminator further includes a plurality of electrically controllable switches, each of the switches having a first port coupled to the voltage regulator and a second port coupled to the first terminal of a corresponding one of the resistive networks wherein each of the switches couple the corresponding resistive network to the voltage regulator when the corresponding switch is in a first state and wherein each of the switches disconnect the corresponding resistive network from the voltage regulator when the corresponding switch is in a second state.

Abstract: A load current sharing circuit is disclosed that allows multiple independent power modules, either switching or linear, to be connected in a parallel configuration such that each module delivers only its proportionate share of the load current. Each module measures the common output voltage, compares that voltage to an internal reference voltage signal, and generates an error voltage signal to be used as feedback for regulating its output voltage. The internal reference voltage signal is a function of the extent to which the current within each module differs from the current of the module with the highest current. That module functions as the master, and all the other modules act as slaves. Each slave increases its share of the load current so as to asymptotically approach the load current of the master to within a preset offset voltage, while the load current of the master decreases.

Abstract: A pulse width modulation comparator having internal latching and resetting functions. The comparator includes a differential input stage having first and second outputs which are connected to supply first and second transistors in a voltage gain stage, respectively. The first output of the input stage drives both of the transistors of the voltage gain stage. The second output of the input stage is connected to drive an output transistor as well as to supply the second transistor of the voltage gain stage. The output of the output transistor is connected via feedback circuitry to drive the transistors of the voltage gain stage. A shunt transistor forms part of the feedback circuit and serves to divert the feedback signal from the voltage gain stage transistors upon the application of a clock reset pulse.An analog voltage is applied to one input of the input stage and a ramp or triangular waveform is applied to the other input.