Patents by Inventor Robert A. Miller, JR.
Robert A. Miller, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240302995Abstract: Dynamic memory area configuration includes designating a portion of memory as a specialized memory unit, and reserving a first portion of specialized memory unit for a plurality of page frame table entries (PFTEs) representing a plurality of frames in the specialized memory. One or more of the PFTEs are stored in respective queue entries within a queue in a reserved area of the specialized memory unit. A particular queue entry indicates that a particular PFTE associated with a particular frame is available for use. An offline request to take a second portion of the specialized memory unit offline is received. Whether to fulfill the offline request is determined based on whether the second portion of the specialized memory unit has an associated queue entry within the queue indicating that the associated frame is not in use back a portion of a page frame table (PFT) or the specialized memory unit.Type: ApplicationFiled: March 10, 2023Publication date: September 12, 2024Inventors: HARRIS M. MORGENSTERN, DAVID HOM, ROBERT MILLER, JR.
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Patent number: 12001328Abstract: A transient input/output in progress state is established during processing of a testcase by a test infrastructure in a computing environment. The method includes obtaining the testcase for an object having one or more pages, and processing the testcase by the test infrastructure. Processing the testcase by the test infrastructure includes, for a page of the object, generating a delay in the processing of the testcase for the page of the object. The delay opens a transient input/output in progress state during which one or more test operations reference the page of the object.Type: GrantFiled: April 5, 2023Date of Patent: June 4, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Miller, Jr., Harris M. Morgenstern, Charles Eugene Mari, Christopher Lee Wood, Alfred Francis Foster
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Patent number: 11726904Abstract: A transient input/output in progress state is established during processing of an input/output testcase by a test infrastructure in a computing environment. The method includes obtaining the input/output testcase for an object having one or more pages, and processing the input/output testcase by the test infrastructure. Processing the input/output testcase by the test infrastructure includes, for a page of the object, generating a delay in the processing of the input/output testcase for the page of the object. The delay opens a transient input/output in progress state during which one or more concurrent test operations are to reference the page of the object.Type: GrantFiled: September 23, 2021Date of Patent: August 15, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Miller, Jr., Harris M. Morgenstern, Charles Eugene Mari, Christopher Lee Wood, Alfred Francis Foster
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Publication number: 20230236959Abstract: A transient input/output in progress state is established during processing of a testcase by a test infrastructure in a computing environment. The method includes obtaining the testcase for an object having one or more pages, and processing the testcase by the test infrastructure. Processing the testcase by the test infrastructure includes, for a page of the object, generating a delay in the processing of the testcase for the page of the object. The delay opens a transient input/output in progress state during which one or more test operations reference the page of the object.Type: ApplicationFiled: April 5, 2023Publication date: July 27, 2023Inventors: Robert MILLER, JR., Harris M. MORGENSTERN, Charles Eugene MARI, Christopher Lee WOOD, Alfred Francis FOSTER
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Publication number: 20230086432Abstract: A transient input/output in progress state is established during processing of an input/output testcase by a test infrastructure in a computing environment. The method includes obtaining the input/output testcase for an object having one or more pages, and processing the input/output testcase by the test infrastructure. Processing the input/output testcase by the test infrastructure includes, for a page of the object, generating a delay in the processing of the input/output testcase for the page of the object. The delay opens a transient input/output in progress state during which one or more concurrent test operations are to reference the page of the object.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Robert MILLER, JR., Harris M. MORGENSTERN, Charles Eugene MARI, Christopher Lee WOOD, Alfred Francis FOSTER
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Patent number: 11048618Abstract: Examples of techniques for environment modification for software application testing are described herein. An aspect includes, based on starting testing of an application under test using a test case in a testing environment and determining that modification of the testing environment is enabled, modifying the testing environment. Another aspect includes running the testing of the application under test using the test case in the modified testing environment. Another aspect includes, based on detection of an error during the testing of the application under test, determining whether the error was caused by the modified testing environment. Another aspect includes, based on determining that the error was caused by the modified testing environment, suppressing the error and continuing the testing of the application under test in the modified testing environment. Another aspect includes, based on determining that the error was not caused by the modified testing environment, percolating the error.Type: GrantFiled: March 11, 2019Date of Patent: June 29, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Partlow, Joseph Griesemer, Robert Miller, Jr.
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Patent number: 11048576Abstract: A computing system includes a processor in signal communication with a memory unit. A test case and recovery (TCR) system is configured to operate in a first mode to perform recovery and repair operations on the memory unit in response to detecting an error event and a second mode to perform test case analysis and verification of an operating system stored in the memory unit in response to being called by a test case.Type: GrantFiled: April 22, 2019Date of Patent: June 29, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harris Morgenstern, Robert Miller, Jr., Tracy Christie, Joseph Danieli
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Publication number: 20200334094Abstract: A computing system includes a processor in signal communication with a memory unit. A test case and recovery (TCR) system is configured to operate in a first mode to perform recovery and repair operations on the memory unit in response to detecting an error event and a second mode to perform test case analysis and verification of an operating system stored in the memory unit in response to being called by a test case.Type: ApplicationFiled: April 22, 2019Publication date: October 22, 2020Inventors: Harris Morgenstern, Robert Miller, JR., Tracy Christie, Joseph Danieli
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Publication number: 20200293430Abstract: Examples of techniques for environment modification for software application testing are described herein. An aspect includes, based on starting testing of an application under test using a test case in a testing environment, determining whether modification of the testing environment is enabled. Another aspect includes, based on determining that modification of the testing environment is enabled, modifying the testing environment.Type: ApplicationFiled: March 11, 2019Publication date: September 17, 2020Inventors: Steven Partlow, Joseph Griesemer, Robert Miller, JR.
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Patent number: 10372091Abstract: An energy dissipating article of manufacture is disclosed that is a high pressure enhanced structure technology comprising a structure having at least one wall forming a sealed inner chamber, and either (i) the sealed inner chamber is filled with a gas under pressure, or (ii) an inflated bladder filled with gas is located within the sealed inner chamber, or (iii) a deflated bladder that is located within the sealed inner chamber, and an inflation system that produces a gas to inflate the deflated bladder, or (iv) the sealed inner chamber at one atmosphere standard normal pressure, and an inflation system that produces a gas, to pressurize the inner chamber. A method of making the articles of manufacture and uses thereof are disclosed.Type: GrantFiled: April 16, 2015Date of Patent: August 6, 2019Inventor: Robert A. Miller, Jr.
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Patent number: 10254962Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.Type: GrantFiled: May 31, 2018Date of Patent: April 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
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Patent number: 10168960Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.Type: GrantFiled: November 14, 2017Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Miller, Jr., Harris M. Morgenstern, James H. Mulder, Elpida Tzortzatos, Dieter Wellerdiek
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Patent number: 10108466Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.Type: GrantFiled: June 29, 2015Date of Patent: October 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Hom, Charles E. Mari, Robert Miller, Jr., Harris M. Morgenstern, Elpida Tzortzatos
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Publication number: 20180275879Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.Type: ApplicationFiled: May 31, 2018Publication date: September 27, 2018Inventors: Robert Miller, JR., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
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Patent number: 10031694Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.Type: GrantFiled: September 29, 2015Date of Patent: July 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
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Publication number: 20180088868Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.Type: ApplicationFiled: November 14, 2017Publication date: March 29, 2018Inventors: ROBERT MILLER, JR., HARRIS M. MORGENSTERN, JAMES H. MULDER, ELPIDA TZORTZATOS, DIETER WELLERDIEK
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Patent number: 9898226Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.Type: GrantFiled: October 28, 2015Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Miller, Jr., Harris M. Morgenstern, James H. Mulder, Elpida Tzortzatos, Dieter Wellerdiek
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Patent number: 9740605Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.Type: GrantFiled: August 26, 2016Date of Patent: August 22, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Miller, Jr., Harris M. Morgenstern, James H. Mulder, Elpida Tzortzatos, Dieter Wellerdiek
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Patent number: 9690483Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.Type: GrantFiled: January 5, 2017Date of Patent: June 27, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
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Publication number: 20170123966Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.Type: ApplicationFiled: August 26, 2016Publication date: May 4, 2017Inventors: ROBERT MILLER, JR., HARRIS M. MORGENSTERN, JAMES H. MULDER, ELPIDA TZORTZATOS, DIETER WELLERDIEK