Abstract: Systems and methods for generating a video of a user-defined virtual reality scene are disclosed. Exemplary implementations may: obtain a scene definition; obtain camera information for multiple virtual cameras to be used in generating a two-dimensional presentation of the virtual reality scene; execute a simulation of the virtual reality scene from the scene definition for at least a portion of the scene duration; obtain camera timing instructions specifying which of the virtual cameras should be used to generate the two-dimensional presentation of the virtual reality scene as a function of progress through the scene duration; generate the two-dimensional presentation of the virtual reality scene in accordance with the camera timing instructions and the camera information.

Abstract: The present disclosure relates to systems, methods, and computer-readable media for managing a cooling system to based on dynamic power and temperature conditions of computing hardware (e.g., a system on a chip (SOC), respective hardware blocks on the SOC). For example, systems described herein involve tracking real-time power and temperature conditions of computing hardware and determining a dynamic cooling level to actuate in maintaining a desired temperature of the computing hardware. This is done in a way that preserves long-term durability of the cooling system while maintaining the ability of the cooling system to respond to a potential spike in power consumption by the computing hardware.

Abstract: A computing device is provided, including one or more processing devices, one or more temperature sensors, a fan, and a fan tachometer. The one or more processing devices may be configured to execute an application program. While executing the application program, the one or more processing devices may be further configured to collect performance data including temperature data received from the one or more temperature sensors and fan speed data received from the fan tachometer. The one or more processing devices may be further configured to generate a fan control signal at least in part by applying a machine learning model to the performance data. The one or more processing devices may be further configured to control the fan according to the fan control signal.

Abstract: A computing device is provided, including one or more processing devices, one or more temperature sensors, a fan, and a fan tachometer. The one or more processing devices may be configured to execute an application program. While executing the application program, the one or more processing devices may be further configured to collect performance data including temperature data received from the one or more temperature sensors and fan speed data received from the fan tachometer. The one or more processing devices may be further configured to generate a fan control signal at least in part by applying a machine learning model to the performance data. The one or more processing devices may be further configured to control the fan according to the fan control signal.

Abstract: The present disclosure relates to a computer-implemented method, devices and systems for determining a location associated with a gemstone. That method includes training a data model to detect a characteristic associated with a feature of interest pertaining to a gemstones surface. The training including the steps of providing a plurality of training images of gemstones, each training image associated with a label for a feature of interest pertaining to a given region of a gemstone type and an output indicating the specific gemstone type for the label.

Abstract: A computing device is provided, including one or more processing devices, one or more temperature sensors, a fan, and a fan tachometer. The one or more processing devices may be configured to execute an application program. While executing the application program, the one or more processing devices may be further configured to collect performance data including temperature data received from the one or more temperature sensors and fan speed data received from the fan tachometer. The one or more processing devices may be further configured to generate a fan control signal at least in part by applying a machine learning model to the performance data. The one or more processing devices may be further configured to control the fan according to the fan control signal.

Abstract: A wet electrolytic capacitor that includes an anode, cathode, and an electrolyte is provided. The cathode contains a substrate and a coating overlying the substrate. The coating comprises a sintered body containing carbonaceous particles (e.g., activated carbon) and inorganic particles (e.g., NbO2).

Abstract: A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match.

Abstract: A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match.

Abstract: A temperature stabilized, constant current source of the present invention includes a feedback control stage that provides a substantially constant battery charging current at a particular temperature. A temperature stabilized current source stage includes a negative temperature coefficient current source that provides a countervailing control current to a positive temperature coefficient current source that is coupled from a sensing resistor. The temperature dependencies of the positive and negative temperature coefficient current sources tend to cancel each other out so as to provide a temperature stabilized current to the sensing resistor. In this way, a control voltage is developed across the control resistor that is independent of resistor temperature dependencies.

Abstract: A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match.

Abstract: A preferred embodiment of an integrated semiconductor device includes a semiconductor die having a hole therethrough. A paddle member includes a handle member connected between the paddle member and the semiconductor die to suspend the paddle member in the hole. A cap layer is bonded to the semiconductor die to completely cover the hole, the paddle member, and the handle member. The second surface of the semiconductor die is bonded to the lead frame.

Abstract: A protection circuit for a semiconductor switch for switching a load is disclosed. Control circuitry is used for switching the semiconductor switch on in response to a switching signal and for switching the semiconductor switch off in response to a deactivation signal. A deactivation circuit is used for generating the deactivation signal. An overvoltage detector circuit responsive to a voltage at an output of the semiconductor switch that exceeds a predetermined value is used for generating an overvoltage signal. The overvoltage detector circuit includes a Zener diode that has its cathode coupled through a resistor to the output of the semiconductor switch and its anode coupled to the collector of the diode connected transistor. A first logic circuit is used for causing the deactivation circuit to generate the deactivation signal in response to the switching signal and the overvoltage signal.

Abstract: A protection circuit for a semiconductor switch for switching a load is disclosed. Control circuitry is used for switching the semiconductor switch on in response to a switching signal and for switching the semiconductor switch off in response to a deactivation signal. A deactivation circuit is used for generating the deactivation signal. An overvoltage detector circuit responsive to a voltage at an output of the semiconductor switch that exceeds a predetermined value is used for generating an overvoltage signal. The overvoltage detector circuit includes a Zener diode that has its cathode coupled through a resistor to the output of the semiconductor switch and its anode coupled to the collector of the diode connected transistor. A first logic circuit is used for causing the deactivation circuit to generate the deactivation signal in response to the switching signal and the overvoltage signal.

Abstract: A preferred embodiment of an integrated semiconductor device includes a semiconductor die having a hole therethrough. A paddle member includes a handle member connected between the paddle member and the semiconductor die to suspend the paddle member in the hole. A cap layer is bonded to the semiconductor die to completely cover the hole, the paddle member, and the handle member. The second surface of the semiconductor die is bonded to the lead frame.

Abstract: An integrated circuit is shown in which provision is made for terminating or locking out the operating circuitry when the supply voltage has fallen below a level that can cause anomalous or unreliable operation. Certain selected transistors are provided with saturation sensors which operate to produce a current when the transistors go into collector saturation. When any of the sensors indicates the onset of saturation, clamping circuitry is energized to provide lock out. In addition, a temperature compensated dummy bandgap circuit is included to sense extremely low supply voltages and provide the lockout function under conditions where a reliable saturation indication might not be available.

Abstract: A voltage regulator circuit is set forth in which the series pass transistor has its high impedance (collector/drain) electrode connected to the output terminal and a shunt transistor has its low impedance (emitter/source) electrode connected to the output terminal. The circuit is arranged to ensure that the shunt transistor is always conductive so that its low impedance electrode will stabilize the operation of the circuit without requiring any external components. The circuit can be fabricated in either bipolar or CMOS form and a low dropout configuration is employed.

Abstract: An integrated circuit is disclosed having a thermal shutdown capability. A single chip bonding pad is coupled to a circuit that will operate the bonding pad at a low potential for normal conditions and will pull it high when a temperature threshold is crossed. Thus, the normally low bonding pad provides a temperature flag. The bonding pad is also coupled to a latch that will hold it high and to a lockout circuit that acts to disable the heat producing chip circuitry. Therefore, when the bonding pad is once driven high the circuits are locked out and will remain out until a start up command is present. This is achieved by either momentarily removing the power supply or by pulling the bonding pad low. Both manual and computer control of the circuit is disclosed.

Abstract: An isolation diffusion process monitor is disclosed. A monitor resistor which has one end terminated in an isolation diffusion region is measured during the wafer fabrication process. Its value will be a function of the lateral surface extent of the isolation diffusion.

Abstract: A circuit is described for trimming a monolithic PN junction isolated silicon IC. The value of a moderate value resistance network is translated to a current that can be made to have a predetermined temperature coefficient and can be applied to the IC. A voltage regulator is shown in which the output voltage and the temperature coefficient can be independently adjusted both at wafer sort and after assembly.