Patents by Inventor Robert A. Pease

Robert A. Pease has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220309717
    Abstract: Systems and methods for generating a video of a user-defined virtual reality scene are disclosed. Exemplary implementations may: obtain a scene definition; obtain camera information for multiple virtual cameras to be used in generating a two-dimensional presentation of the virtual reality scene; execute a simulation of the virtual reality scene from the scene definition for at least a portion of the scene duration; obtain camera timing instructions specifying which of the virtual cameras should be used to generate the two-dimensional presentation of the virtual reality scene as a function of progress through the scene duration; generate the two-dimensional presentation of the virtual reality scene in accordance with the camera timing instructions and the camera information.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Inventors: Gil Baron, Daniel Andrew Bellezza, Jeffrey Scott Dixon, William Stuart Farquhar, Jason Zesheng Hwang, John Henry Kanikula Peters, Nhan Van Khong, Christopher Robert Laubach, Gregory Scott Pease, Jonathan Michael Ross
  • Patent number: 11403785
    Abstract: Systems and methods for generating a video of a user-defined virtual reality scene are disclosed. Exemplary implementations may: obtain a scene definition; obtain camera information for multiple virtual cameras to be used in generating a two-dimensional presentation of the virtual reality scene; execute a simulation of the virtual reality scene from the scene definition for at least a portion of the scene duration; obtain camera timing instructions specifying which of the virtual cameras should be used to generate the two-dimensional presentation of the virtual reality scene as a function of progress through the scene duration; generate the two-dimensional presentation of the virtual reality scene in accordance with the camera timing instructions and the camera information.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: August 2, 2022
    Assignee: Mindshow Inc.
    Inventors: Gil Baron, Daniel Andrew Bellezza, Jeffrey Scott Dixon, William Stuart Farquhar, Jason Zesheng Hwang, John Henry Kanikula Peters, Nhan Van Khong, Christopher Robert Laubach, Gregory Scott Pease, Jonathan Michael Ross
  • Publication number: 20070211413
    Abstract: A wet electrolytic capacitor that includes an anode, cathode, and an electrolyte is provided. The cathode contains a substrate and a coating overlying the substrate. The coating comprises a sintered body containing carbonaceous particles (e.g., activated carbon) and inorganic particles (e.g., NbO2).
    Type: Application
    Filed: March 9, 2006
    Publication date: September 13, 2007
    Inventors: James Fife, Gang Ning, Zebbie Sebald, James Bates, Robert Pease
  • Patent number: 6313692
    Abstract: A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match.
    Type: Grant
    Filed: July 8, 2000
    Date of Patent: November 6, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Robert A. Pease
  • Patent number: 6249176
    Abstract: A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: June 19, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Robert A. Pease
  • Patent number: 6225787
    Abstract: A temperature stabilized, constant current source of the present invention includes a feedback control stage that provides a substantially constant battery charging current at a particular temperature. A temperature stabilized current source stage includes a negative temperature coefficient current source that provides a countervailing control current to a positive temperature coefficient current source that is coupled from a sensing resistor. The temperature dependencies of the positive and negative temperature coefficient current sources tend to cancel each other out so as to provide a temperature stabilized current to the sensing resistor. In this way, a control voltage is developed across the control resistor that is independent of resistor temperature dependencies.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: May 1, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Sean S. Chen, Robert Pease
  • Patent number: 6124753
    Abstract: A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: September 26, 2000
    Inventor: Robert A. Pease
  • Patent number: 5583373
    Abstract: A preferred embodiment of an integrated semiconductor device includes a semiconductor die having a hole therethrough. A paddle member includes a handle member connected between the paddle member and the semiconductor die to suspend the paddle member in the hole. A cap layer is bonded to the semiconductor die to completely cover the hole, the paddle member, and the handle member. The second surface of the semiconductor die is bonded to the lead frame.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: December 10, 1996
    Assignee: National Semiconductor Corporation
    Inventors: James V. Ball, Robert A. Pease
  • Patent number: 5546260
    Abstract: A protection circuit for a semiconductor switch for switching a load is disclosed. Control circuitry is used for switching the semiconductor switch on in response to a switching signal and for switching the semiconductor switch off in response to a deactivation signal. A deactivation circuit is used for generating the deactivation signal. An overvoltage detector circuit responsive to a voltage at an output of the semiconductor switch that exceeds a predetermined value is used for generating an overvoltage signal. The overvoltage detector circuit includes a Zener diode that has its cathode coupled through a resistor to the output of the semiconductor switch and its anode coupled to the collector of the diode connected transistor. A first logic circuit is used for causing the deactivation circuit to generate the deactivation signal in response to the switching signal and the overvoltage signal.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: August 13, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Robert A. Pease, Robin Shields
  • Patent number: 5537064
    Abstract: A protection circuit for a semiconductor switch for switching a load is disclosed. Control circuitry is used for switching the semiconductor switch on in response to a switching signal and for switching the semiconductor switch off in response to a deactivation signal. A deactivation circuit is used for generating the deactivation signal. An overvoltage detector circuit responsive to a voltage at an output of the semiconductor switch that exceeds a predetermined value is used for generating an overvoltage signal. The overvoltage detector circuit includes a Zener diode that has its cathode coupled through a resistor to the output of the semiconductor switch and its anode coupled to the collector of the diode connected transistor. A first logic circuit is used for causing the deactivation circuit to generate the deactivation signal in response to the switching signal and the overvoltage signal.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: July 16, 1996
    Assignee: National Semiconductor Corp.
    Inventors: Robert A. Pease, Robin Shields
  • Patent number: 5508231
    Abstract: A preferred embodiment of an integrated semiconductor device includes a semiconductor die having a hole therethrough. A paddle member includes a handle member connected between the paddle member and the semiconductor die to suspend the paddle member in the hole. A cap layer is bonded to the semiconductor die to completely cover the hole, the paddle member, and the handle member. The second surface of the semiconductor die is bonded to the lead frame.
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: April 16, 1996
    Assignee: National Semiconductor Corporation
    Inventors: James V. Ball, Robert A. Pease
  • Patent number: 5122920
    Abstract: An integrated circuit is shown in which provision is made for terminating or locking out the operating circuitry when the supply voltage has fallen below a level that can cause anomalous or unreliable operation. Certain selected transistors are provided with saturation sensors which operate to produce a current when the transistors go into collector saturation. When any of the sensors indicates the onset of saturation, clamping circuitry is energized to provide lock out. In addition, a temperature compensated dummy bandgap circuit is included to sense extremely low supply voltages and provide the lockout function under conditions where a reliable saturation indication might not be available.
    Type: Grant
    Filed: August 22, 1988
    Date of Patent: June 16, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Robert A. Pease
  • Patent number: 4928056
    Abstract: A voltage regulator circuit is set forth in which the series pass transistor has its high impedance (collector/drain) electrode connected to the output terminal and a shunt transistor has its low impedance (emitter/source) electrode connected to the output terminal. The circuit is arranged to ensure that the shunt transistor is always conductive so that its low impedance electrode will stabilize the operation of the circuit without requiring any external components. The circuit can be fabricated in either bipolar or CMOS form and a low dropout configuration is employed.
    Type: Grant
    Filed: October 6, 1988
    Date of Patent: May 22, 1990
    Assignee: National Semiconductor Corporation
    Inventor: Robert A. Pease
  • Patent number: 4907117
    Abstract: An integrated circuit is disclosed having a thermal shutdown capability. A single chip bonding pad is coupled to a circuit that will operate the bonding pad at a low potential for normal conditions and will pull it high when a temperature threshold is crossed. Thus, the normally low bonding pad provides a temperature flag. The bonding pad is also coupled to a latch that will hold it high and to a lockout circuit that acts to disable the heat producing chip circuitry. Therefore, when the bonding pad is once driven high the circuits are locked out and will remain out until a start up command is present. This is achieved by either momentarily removing the power supply or by pulling the bonding pad low. Both manual and computer control of the circuit is disclosed.
    Type: Grant
    Filed: September 8, 1988
    Date of Patent: March 6, 1990
    Assignee: National Semiconductor Corporation
    Inventors: Robert A. Pease, Mansour Izadinia, Jonathan Klein
  • Patent number: 4701779
    Abstract: An isolation diffusion process monitor is disclosed. A monitor resistor which has one end terminated in an isolation diffusion region is measured during the wafer fabrication process. Its value will be a function of the lateral surface extent of the isolation diffusion.
    Type: Grant
    Filed: November 5, 1984
    Date of Patent: October 20, 1987
    Assignee: National Semiconductor Corporation
    Inventor: Robert A. Pease
  • Patent number: 4665356
    Abstract: A circuit is described for trimming a monolithic PN junction isolated silicon IC. The value of a moderate value resistance network is translated to a current that can be made to have a predetermined temperature coefficient and can be applied to the IC. A voltage regulator is shown in which the output voltage and the temperature coefficient can be independently adjusted both at wafer sort and after assembly.
    Type: Grant
    Filed: January 27, 1986
    Date of Patent: May 12, 1987
    Assignee: National Semiconductor Corporation
    Inventor: Robert A. Pease
  • Patent number: 4176308
    Abstract: A voltage regulator including a current regulator for maintaining predetermined currents in the voltage regulator is disclosed. The voltage regulator includes an output terminal for providing an output voltage; an adjustment terminal; and a control circuit connected to the output terminal at a level that differs from the voltage at the adjustment terminal by a predetermined voltage difference. The control circuit of the voltage regulator includes a resistive divider coupled between the output terminal and the adjustment terminal; a pair of transistors having their collectors connected in common and their bases respectively coupled to the resistive divider to provide a portion of the voltage difference between the output terminal and the adjustment terminal across their bases.
    Type: Grant
    Filed: September 21, 1977
    Date of Patent: November 27, 1979
    Assignee: National Semiconductor Corporation
    Inventors: Robert C. Dobkin, Robert A. Pease
  • Patent number: 3995304
    Abstract: A monolithic integrated circuit having a plurality of transistors arranged in groups to comprise sources of binary weighted currents, each group being disposed about a common center of distribution, so as to minimize thermal perturbations of transistor function.
    Type: Grant
    Filed: January 10, 1972
    Date of Patent: November 30, 1976
    Assignee: Teledyne, Inc.
    Inventor: Robert A. Pease