Abstract: The present invention provides circuitry which facilitates user selection of alternative memory accessing techniques. The present invention provides a design approach or technique to transform the time associated with waiting for a valid "way-select" signal into cycle reduction time, thus providing a beneficial increase in the overall performance of multi-way associative cache and memory designs.

Abstract: A dynamic latch circuit design minimizes set and restore power without sacrificing speed. The dynamic latch circuit provides two significant power saving advantages over traditional dynamic latch designs. The first regulates dynamic restore power with the state of the latch. If the dynamic internal node of the latch has not been discharged, then the restore signal applied to the input of the latch is not transferred to the restore device attached to the node. By isolating the restore device under these conditions, additional power is not wasted boot-strapping up the already precharged node. Second, by design, the restore path and set path are separate. The input signals used to set the latch are different and isolated from those performing the restore. Therefore, there is no conducting path between the voltage source and circuit ground as the restore device turns on.

Abstract: A memory system having a read/write head is provided wherein a system clock or a test clock can be used to initiate a pulse for enabling the read/write head during a write period and a delay circuit coupled to the system clock or to the test clock can be used to terminate the enabling or control pulse, with a write clock having an input coupled to the system clock also used to terminate the enabling or control pulse during a write period.

Abstract: A memory system is provided wherein array signals begin at the start of a first phase of a system clock and a sense amplifier set signal is developed during a second phase of the system clock which includes an array of memory cells including word lines and bit lines, word drivers connected to the word lines, a word address decoder enabled by the first phase of the clock system and coupled to the word drivers, a bit switch coupling a bit line to a sense amplifier, a system clock inverting circuit, a timing circuit having a first input connected to a late select signal, a second input connected to the inverting circuit and an output connected to the bit switch and a delay circuit having an input coupled to the inverting circuit and an output connected to the sense amplifier.