Abstract: A digital timing recovery circuit for rapid acquisition and synchronization of sampling clock phase in a data playback signal processing channel. The filtered playback signal in a (1,7)ML coded playback channel is sampled at the rate of one sample per bit window and the digitized sample values are processed with a (1,7)ML decoding procedure to produce decoded bits. A digital timing recovery circuit of this invention uses the digitized sample values directly to control the sampling clock phase by computing a digital phase error signal (PES) that is a constant function of phase error independent of data pattern. The PES depends only on the adjacent samples before and after a peak signal value. These "side-samples" contain maximal timing information because they occur at the steepest slope of the read-back signal and are thus most sensitive to clock phase error.

Abstract: To improve data detection reliability in a coded maximum likelihood signal processing channel, two counters count the number of times actual values of linear functions of digital sample values corresponding to one and another preselected data patterns are within m units above and m units below, respectively, a preselected decision boundary used to determine whether detected data corresponding to a coded sequence of runlength limited code is a "1" or a "0". A difference count has a magnitude and sign denoting difference between counts in the two counters. After N occurrences of each preselected data pattern irrespective of how far from the boundary, the boundary is adjusted upwardly or downwardly, provided the difference count at least equals +S or at most -S, respectively.

Abstract: Decoder for processing digital sample values corresponding to an incoming read signal representative of coded binary data. Functional expressions of digital sample values are precomputed for a preselected number of sample values ahead of a current sample value. To provide binary decision outputs, preselected functional expressions are compared against binary representations of corresponding thresholds that are conditioned by the sign of a selected functional expression comprising at least one preselected digital sample value. These outputs, the sign of the selected functional expression, the current value and previous value of decoded data, and the current value of detected phase, are all used to determine the next value of decoded data and next value of detected phase. These next values become the current values of decoded data and detected phase for the next clock cycle.

Abstract: A direct access storage device (DASD) system uses a read/write head having a wide transducer write element and a narrow magneto-resistive read element. In order to avoid mistakenly reading a incompletely erased old data field, the system uses a verification procedure. Data are read at two positions along the data track which are separated by a radial distance D. This distance D is selected to be greater than the width of any incompletely erased data record. If the data read at the two read positions are equal, then the data are deemed to be correct and are sent to a host system.

Abstract: A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved.

Abstract: A method for processing, in a signal processing channel, digital values corresponding to a digitized incoming analog signal representative of coded binary data. A state-dependent sequence detection algorithm includes two groups of appropriate functional expressions of digital sample values, which expressions are identical but offset one sample position from each other. During each iterating step with successive pairs of clock cycles, the value of each expression in the two groups of expressions is precomputed from a preselected number of sample values ahead of a then current sample value; preselected ones of these expression values are compared against an appropriate threshold, which is the same for corresponding expressions of each group, to provide respective binary decision outputs corresponding to each of the two groups; and the current state value then advances to two next successive state values.

Abstract: Method and circuitry for phase synchronizing an analog input signal with a clock signal by sensing clock delay error, adjusting in increments clock delay trim of a delay element that initially has an arbitrary delay setting, and stopping adjustment after differential delay between the signals has been eliminated.

Abstract: This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations:P.sub.8.sup.a = i.sub.8.sup.a .sym.i.sub.8.sup.b .sym.i.sub.6.sup.b .sym.i.sub.1.sup.b .sym.i.sub.3.sup.c .sym.i.sub.2.sup.cP.sub.8.sup.b = i.sub.8.sup.a .sym.i.sub.6.sup.a .sym.i.sub.3.sup.a .sym.i.sub.5.sup.b .sym.i.sub.8.sup.c .sym.i.sub.4.sup.cwhere i.sub.8.sup.a, i.sub.8.sup.b and i.sub.8.sup.c are the three information bits in the set associated with the parity bits P.sub.8.sup.a and P.sub.8.sup.b while the other information bits are from the seven sets of the sequence preceding the set associated with the parity bits.