Abstract: The disclosed embodiments are directed to a wearable automatic drug delivery device configured to provide basal-only dosing of insulin. In a primary embodiment, the wearable drug delivery device is configured to provide automatic operation and provides audible alerts and visual status indicators to the patient. In other embodiments, the patient may have some degree of control over the operation of the device by providing tapping gestures on housing of the device. In yet another embodiment, the patient may provide input and receive status from the device via an application executing on a portable computing device in wireless communication with the wearable drug delivery device.

Abstract: A data processor includes an input/output bridge that provides enforcement of a security status on transactions between devices across the bridge. The bridge includes circuitry to parse a received request to obtain one or more identifiers, and compare the identifiers against one or more programmable lookup tables. Based on this comparison, the bridge can determine the security status of the transaction, as well as selectively forward the transaction based on the security status.

Abstract: An arbiter circuit manages and enforces arbitration and quality of service (QOS) among multiple devices accessing a resource, such as a memory. The arbiter circuit receives requests from a number of devices to use resources of a bridge connecting to a memory, and maintains a count of bridge resources available on a per-device and per-bus basis. The arbiter circuit operates to select a next one of the requests to grant a bridge resource based on the device originating the request, a count of the per-device resources available, and a count of the resources available to the bus connecting the device to the bridge.

Abstract: A circuit manages and controls access requests to a register, such as a control and status register (CSR) among a number of devices. In particular, the circuit selectively forwards or suspends off-chip access requests and forwards on-chip access requests independent of the status of off-chip requests. The circuit receives access requests at a plurality of buses, one or more of which can be dedicated to exclusively on-chip requests and/or exclusively off-chip requests. Based on the completion status of previous off-chip access requests, further off-chip access requests are selectively forwarded or suspended, while on-chip access request are sent independently of off-chip request status.

Abstract: In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.

Abstract: An input/output bridge controls access to a memory by a number of devices. The bridge enforces ordering of access requests according to a register storing an order configuration, which can be programmed to accommodate a given application. When suspending an access request as a result of enforcing an order configuration, the bridge may also cause a prefetch at the memory for the suspended access request. Subsequently, following the completion of a previous access request meeting the order configuration, the suspended access request is released. Due to the prefetch, an access operation can be completed with minimal delay.

Abstract: Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor.

Abstract: In an embodiment, a method for managing access to memory includes receiving requests for access to a memory from one or more devices, each particular request associated with one of a plurality of virtual channels. A tag is assigned to each request received. Each tag assigned is added to a linked list associated with the corresponding virtual channel. Each request received with the assigned tag is transmitted to the memory. Responses to the requests are received from the memory, each response having an associated tag, and the responses received are sent to the one or more devices based on the corresponding linked list and the corresponding tag.

Abstract: An input/output bridge controls access to a memory by a number of devices and maintains an order of access requests under virtualization. In particular, the bridge manages and enforces order among multiple independent threads of requests to a memory. The bridge populates a number of ordered lists with received access requests based on a corresponding identifier of each access request. A top list is also maintained, where the top list is populated with access requests and a corresponding translated physical address. The bridge forwards access requests from the top list, maintaining the order of each of the independent threads.

Abstract: An arbiter circuit manages and enforces arbitration and quality of service (QOS) among multiple devices accessing a resource, such as a memory. The arbiter circuit receives requests from a number of devices to use resources of a bridge connecting to a memory, and maintains a count of bridge resources available on a per-device and per-bus basis. The arbiter circuit operates to select a next one of the requests to grant a bridge resource based on the device originating the request, a count of the per-device resources available, and a count of the resources available to the bus connecting the device to the bridge.

Abstract: A data processor includes an input/output bridge that provides enforcement of a security status on transactions between devices across the bridge. The bridge includes circuitry to parse a received request to obtain one or more identifiers, and compare the identifiers against one or more programmable lookup tables. Based on this comparison, the bridge can determine the security status of the transaction, as well as selectively forward the transaction based on the security status.

Abstract: An input/output bridge controls access to a memory by a number of devices. The bridge enforces ordering of access requests according to a register storing an order configuration, which can be programmed to accommodate a given application. When suspending an access request as a result of enforcing an order configuration, the bridge may also cause a prefetch at the memory for the suspended access request. Subsequently, following the completion of a previous access request meeting the order configuration, the suspended access request is released. Due to the prefetch, an access operation can be completed with minimal delay.

Abstract: A circuit manages and controls access requests to a register, such as a control and status register (CSR) among a number of devices. In particular, the circuit selectively forwards or suspends off-chip access requests and forwards on-chip access requests independent of the status of off-chip requests. The circuit receives access requests at a plurality of buses, one or more of which can be dedicated to exclusively on-chip requests and/or exclusively off-chip requests. Based on the completion status of previous off-chip access requests, further off-chip access requests are selectively forwarded or suspended, while on-chip access request are sent independently of off-chip request status.

Abstract: In one embodiment, a system includes reassembly stores configured to store a fragment of a packet in a particular reassembly store corresponding with the packet, and when the particular reassembly store contains fragments of the packet representing the packet as a whole, forward the packet to a plurality of cores. The system further includes a packet reception unit configured to store the fragment in one of a plurality of memories within the reassembly stores, and, when the one of the plurality of memories is filled, copy the at least one fragment to a memory external to the packet reception unit.

Abstract: In one embodiment, a system includes reassembly stores configured to store a fragment of a packet in a particular reassembly store corresponding with the packet, and when the particular reassembly store contains fragments of the packet representing the packet as a whole, forward the packet to a plurality of cores. The system further includes a packet reception unit configured to store the fragment in one of a plurality of memories within the reassembly stores, and, when the one of the plurality of memories is filled, copy the at least one fragment to a memory external to the packet reception unit.

Abstract: A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and IO units in the network services processor. Instead of writing the cache block back to the buffer in memory that will be freed, the input/output bridge issues don't write back commands to a cache controller to clear the dirty bit for the selected cache block, thus avoiding wasteful write-backs from cache to memory. After the dirty bit is cleared, the buffer in memory is freed, that is, made available for allocation to store data for another packet.

Abstract: In an embodiment, a method for managing access to memory includes receiving requests for access to a memory from one or more devices, each particular request associated with one of a plurality of virtual channels. A tag is assigned to each request received. Each tag assigned is added to a linked list associated with the corresponding virtual channel. Each request received with the assigned tag is transmitted to the memory. Responses to the requests are received from the memory, each response having an associated tag, and the responses received are sent to the one or more devices based on the corresponding linked list and the corresponding tag.

Abstract: In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.

Abstract: A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and IO units in the network services processor. Instead of writing the cache block back to the buffer in memory that will be freed, the input/output bridge issues don't write back commands to a cache controller to clear the dirty bit for the selected cache block, thus avoiding wasteful write-backs from cache to memory. After the dirty bit is cleared, the buffer in memory is freed, that is, made available for allocation to store data for another packet.