Patents by Inventor Robert A. Shannon

Robert A. Shannon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947454
    Abstract: Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: April 2, 2024
    Assignee: Ampere Computing LLC
    Inventors: Richard James Shannon, Stephan Jean Jourdan, Matthew Robert Erler, Jared Eric Bendt
  • Patent number: 11732585
    Abstract: Methods, apparatus, and systems for trapped rotatable weights to improve rotor balance are disclosed. An example apparatus includes a lock nut; a rotor assembly; a channel defined by the lock nut and the rotor assembly, the channel wrapped circumferentially around a geometric center of the rotor assembly; and a weight trapped within the channel.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: August 22, 2023
    Assignee: General Electric Company
    Inventors: Robert Allen Hagan, Jason Francis Pepi, Kevin Robert Shannon
  • Publication number: 20220235662
    Abstract: Methods, apparatus, and systems for trapped rotatable weights to improve rotor balance are disclosed. An example apparatus includes a lock nut; a rotor assembly; a channel defined by the lock nut and the rotor assembly, the channel wrapped circumferentially around a geometric center of the rotor assembly; and a weight trapped within the channel.
    Type: Application
    Filed: January 28, 2021
    Publication date: July 28, 2022
    Inventors: Robert Allen Hagan, Jason Francis Pepi, Kevin Robert Shannon
  • Patent number: 11200058
    Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: December 14, 2021
    Inventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon, Lin Wang
  • Patent number: 11074076
    Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: July 27, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon, Lin Wang
  • Patent number: 10989480
    Abstract: A counter-flow heat exchanger is provided that includes: a first fluid path having a first supply tube connected to a first transition area separating the first fluid path into a first array of first passageways, with the first array of first passageways merging at a first converging area into a first discharge tube; and a second fluid path having a second supply tube connected to a second transition area separating the second fluid path into a second array of second passageways, with the second array of second passageways merge at a second converging area into a second discharge tube. The first passageways and the second passageways have a substantially helical path around the centerline of the counter-flow heat exchanger. Additionally, the first array and the second array are arranged together such that each first passageway is adjacent to at least one second passageway.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: April 27, 2021
    Assignee: General Electric Company
    Inventors: Peter Joseph Rock, Jr., Matthew Goldenberg, Lauren Ashley Henning, Jeffrey Miles McMillen Prescott, Kevin Robert Shannon
  • Patent number: 10892907
    Abstract: A home automation (HA) system may include a cloud server, HA operation devices within a senior living facility, and HA user interface devices for respective users within the senior living facility. Each HA user interface device may include a user input device, a display defining a user interface (UI), and a controller. The HA system may include HA hub devices within the senior living facility to provide communications for the cloud server, the HA user interface devices, and the HA operation devices. The controller may send user interaction data to the cloud server and operate the UI according to a user cognitive level. The cloud server may be configured to determine the user cognitive level based upon the user interaction data received from a given HA user interface device, and send the user cognitive level to the given HA user interface device.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 12, 2021
    Assignee: K4CONNECT INC.
    Inventors: Jonathan Andrew Gould, Richard Clancy, Robert Shannon Smith
  • Patent number: 10731484
    Abstract: A high pressure BLISK includes at least one circular row of airfoils circumferentially disposed about, integral with, and extending radially outwardly from an annular rim having an annular flat aft facing face with coplanar radially outer and inner face portions radially separated by an annular undercut extending into the rim from the aft facing face. Airfoil roots including root fillets extend around the airfoil between the rim and pressure and suction sides of the airfoils. An axially aftwardly extending annular cylindrical section extends aftwardly from the flat face. The BLISK being a first of axially adjacent first and second rotor sections connected by a rabbet joint. A forward arm of the second rotor section includes an outer forward facing annular face spaced apart from the aft facing face radially outwardly of the annular undercut and a radially inner forward facing annular face contacting the aft facing face.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: August 4, 2020
    Assignee: General Electric Company
    Inventors: Christopher Mark Bordne, Jason Francis Pepi, Kevin Robert Shannon
  • Publication number: 20200064075
    Abstract: A counter-flow heat exchanger is provided that includes: a first fluid path having a first supply tube connected to a first transition area separating the first fluid path into a first array of first passageways, with the first array of first passageways merging at a first converging area into a first discharge tube; and a second fluid path having a second supply tube connected to a second transition area separating the second fluid path into a second array of second passageways, with the second array of second passageways merge at a second converging area into a second discharge tube. The first passageways and the second passageways have a substantially helical path around the centerline of the counter-flow heat exchanger. Additionally, the first array and the second array are arranged together such that each first passageway is adjacent to at least one second passageway.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Peter Joseph Rock, JR., Matthew Goldenberg, Lauren Ashley Henning, Jeffrey Miles McMillen Prescott, Kevin Robert Shannon
  • Patent number: 10495384
    Abstract: A counter-flow heat exchanger is provided that includes: a first fluid path having a first supply tube connected to a first transition area separating the first fluid path into a first array of first passageways, with the first array of first passageways merging at a first converging area into a first discharge tube; and a second fluid path having a second supply tube connected to a second transition area separating the second fluid path into a second array of second passageways, with the second array of second passageways merge at a second converging area into a second discharge tube. The first passageways and the second passageways have a substantially helical path around the centerline of the counter-flow heat exchanger. Additionally, the first array and the second array are arranged together such that each first passageway is adjacent to at least one second passageway.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: December 3, 2019
    Assignee: General Electric Company
    Inventors: Peter Joseph Rock, Jr., Matthew Goldenberg, Lauren Ashley Henning, Jeffrey Miles McMillen Prescott, Kevin Robert Shannon
  • Publication number: 20190182071
    Abstract: A home automation (HA) system may include a cloud server, HA operation devices within a senior living facility, and HA user interface devices for respective users within the senior living facility. Each HA user interface device may include a user input device, a display defining a user interface (UI), and a controller. The HA system may include HA hub devices within the senior living facility to provide communications for the cloud server, the HA user interface devices, and the HA operation devices. The controller may send user interaction data to the cloud server and operate the UI according to a user cognitive level. The cloud server may be configured to determine the user cognitive level based upon the user interaction data received from a given HA user interface device, and send the user cognitive level to the given HA user interface device.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 13, 2019
    Inventors: Jonathan Andrew Gould, Richard Clancy, Robert Shannon Smith
  • Patent number: 10108933
    Abstract: When a trading system receives a request from an employee to trade leave time for a related value, the trading system communicates with an employer system to request a value of leave time accrued by the employee. The employer system transmits the value of leave time to the trading system, and the trading system converts the value of leave time into a related value. Through the trading system, the employee can use the related value to purchase items from one or more merchants.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: October 23, 2018
    Assignee: PTO, Inc.
    Inventors: Gregory Jon Hatch, Todd Comnenos Lucas, Robert Shannon Whalen, Steven Craig Armstrong
  • Patent number: 10007613
    Abstract: An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 26, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon
  • Publication number: 20170030651
    Abstract: A counter-flow heat exchanger is provided that includes: a first fluid path having a first supply tube connected to a first transition area separating the first fluid path into a first array of first passageways, with the first array of first passageways merging at a first converging area into a first discharge tube; and a second fluid path having a second supply tube connected to a second transition area separating the second fluid path into a second array of second passageways, with the second array of second passageways merge at a second converging area into a second discharge tube. The first passageways and the second passageways have a substantially helical path around the centerline of the counter-flow heat exchanger. Additionally, the first array and the second array are arranged together such that each first passageway is adjacent to at least one second passageway.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 2, 2017
    Inventors: Peter Joseph Rock, JR., Matthew Goldenberg, Lauren Ashley Henning, Jeffrey Miles McMillen Prescott, Kevin Robert Shannon
  • Patent number: 9529727
    Abstract: A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: December 27, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon
  • Publication number: 20160328325
    Abstract: An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 10, 2016
    Inventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon
  • Publication number: 20160138408
    Abstract: A high pressure BLISK includes at least one circular row of airfoils circumferentially disposed about, integral with, and extending radially outwardly from an annular rim having an annular flat aft facing face with coplanar radially outer and inner face portions radially separated by an annular undercut extending into the rim from the aft facing face. Airfoil roots including root fillets extend around the airfoil between the rim and pressure and suction sides of the airfoils. An axially aftwardly extending annular cylindrical section extends aftwardly from the flat face. The BLISK being a first of axially adjacent first and second rotor sections connected by a rabbet joint. A forward arm of the second rotor section includes an outer forward facing annular face spaced apart from the aft facing face radially outwardly of the annular undercut and a radially inner forward facing annular face contacting the aft facing face.
    Type: Application
    Filed: October 22, 2015
    Publication date: May 19, 2016
    Inventors: Christopher Mark BORDNE, Jason Francis Pepi, Kevin Robert SHANNON
  • Publication number: 20160001786
    Abstract: A locomotive crew console includes a chair with a backrest, and a seat and a footrest both foldable with respect to a frame for seated and standing operations, The chair armrest assemblies include locomotive controls. An articulating mount is coupled to an armrest assembly for one or more displays of locomotive information. A rotatable base for the frame allows the chair, the locomotive controls, and the displays to rotate with the chair.
    Type: Application
    Filed: July 2, 2015
    Publication date: January 7, 2016
    Inventors: Amanda M. DiFiore, Norman L. Dana, Robert A. Shannon, Philip O. Bogue, Richard J. Doucette, Abdullatif K. Zaouk
  • Publication number: 20150347308
    Abstract: A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 3, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon
  • Publication number: 20150324239
    Abstract: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.
    Type: Application
    Filed: May 7, 2014
    Publication date: November 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Suresh Kumar Venkumahanti, Stephen Robert Shannon, Lin Wang