Abstract: A user interface for a network security policy monitoring system and method that performs network and security assessments based on system-wide policy, whereby real network traffic is analyzed to identify abnormalities, vulnerabilities, and incorrect configurations by listening on a network, logging events, and taking action.

Abstract: A timer unit that permits individual timer registers to be taken offline from the timer complex. A single register is taken offline instead of checkstopping the entire computer system due to a damaged timer, for example, thereby reducing system outages and thus providing increased availability of the system.

Abstract: The present invention improves the interaction of a virtual memory systems and a garbage collection system, thereby reducing garbage collection effort and improving virtual memory performance. The method includes the steps of: (1) developing a secondary memory (e.g. disk) dirty page map; (2) developing a saved state map from a primary memory (e.g. RAM) dirty page map; (3) using the secondary memory dirty page map and the primary memory dirty page map to effectively reduce the size of the base set; (4) performing a garbage collection routine on at least a segment of the heap based upon the effectively reduced base set; and (5) performing a virtual memory routine using the primary memory dirty page map and the saved state map. The apparatus of the present invention implements the method on a digital computer system with a combination of hardware and software.

Abstract: A digital phase locked loop circuit produces a reference waveform synchronized with a sequence of read data signals by dividing the reference waveform which consists of 0's and 1's windows, into early and late regions for determining the occurrence of a read data pulse within a window. The occurrence of a data pulse during an early or a late region produces a corresponding phase error signal. The phase error signal controls the frequency of the reference signal by increasing or decreasing the periods of the early or late regions to synchronize the reference signal with the sequence of read data signals. A period table is addressed by a combination of reference signal timing and a frequency register whose output is modulated over several cycles.

Abstract: A phase-locked loop (PLL) for use in decoding MFM data recordings. The loop uses a counter to generate timing signals which divide bitcells into data and clock windows and which define times within these windows at which transitions in the MFM signal are expected to occur. Data and clock windows of differing relative size are readily accomodated. The PLL has two synchronization modes: one mode allows the PLL to take maximum advantage of both data and clock transitions which occur when reading actual data; a second mode is used during the synchronization period at the beginning of a data block and allows the PLL to lock quickly yet assure that it will lock to the bit frequency and not lock to harmonics or beat frequencies. A charge pump generates the PLL error signal by responding to pump-up and pump-down control signals which are set and cleared in response to the timing signals from the counter and in response to the detection of transitions in the input signal.