Patents by Inventor Robert A. Southworth

Robert A. Southworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916800
    Abstract: Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: David Arditti Ilitzky, John Greth, Robert Southworth, Karl S. Papadantonakis, Bongjin Jung, Arvind Srinivasan
  • Patent number: 11722438
    Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: John Greth, Arvind Srinivasan, Robert Southworth, David Arditti Ilitzky, Bongjin Jung, Gaspar Mora Porta
  • Patent number: 11700209
    Abstract: Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Robert Southworth, Karl S. Papadantonakis, Mika Nystroem, Arvind Srinivasan, David Arditti Ilitzky, Jonathan Dama
  • Publication number: 20230139762
    Abstract: Examples described herein relate to a network interface device that includes a programmable event processing architecture comprising a plurality of programmable event processors. When the plurality of programmable event processors are operational, one or more of the programmable event processors are to perform memory accesses separate from compute operations, group one or more events into at least one group, enforce atomic processing of other events within a group of the at least one group, wherein the atomic processing comprises propagation of state changes to among events of the group, and perform parallel processing of events belonging to different groups.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Inventors: Stephen IBANEZ, Robert SOUTHWORTH, Salma Mirza JOHNSON, Vered BAR BRACHA, Bradley A. BURRES
  • Patent number: 11641326
    Abstract: Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 2, 2023
    Assignee: Intel Corporation
    Inventors: Karl S. Papadantonakis, Robert Southworth, Arvind Srinivasan, Helia A. Naeimi, James E. McCormick, Jr., Jonathan Dama, Ramakrishna Huggahalli, Roberto Penaranda Cebrian
  • Publication number: 20230127722
    Abstract: Examples described herein relate to a network interface device that includes a programmable event processing architecture that includes a plurality of programmable event processors. In some examples, the plurality of programmable event processors are to perform memory accesses separate from compute operations. In some examples, the plurality of programmable event processors are to group one or more events into at least one group. In some examples, the plurality of programmable event processors are to perform parallel processing of events belonging to different groups. In some examples, the plurality of programmable event processors are programmed to perform at least one transport protocol.
    Type: Application
    Filed: December 27, 2022
    Publication date: April 27, 2023
    Inventors: Stephen IBANEZ, Robert SOUTHWORTH, Salma Mirza JOHNSON, Vered BAR BRACHA, Bradley A. BURRES
  • Publication number: 20230123387
    Abstract: Examples described herein relate to a network interface device that includes circuitry to cause transmission of a packet following transmission of one or more data packets to a receiver, wherein the packet comprises one or more of: a count of transmitted data, a timestamp of transmission of the packet, and/or an index value to one or more of a count of transmitted data and a timestamp of transmission of the packet. In some examples, the network interface device includes circuitry to receive, from the receiver, a second packet that includes a copy of the count of transmitted data and the timestamp of transmission of the packet or the index from the packet. In some examples, the network interface device includes circuitry to perform congestion control based on the received copy of the count of transmitted data and the timestamp of transmission of the packet.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Inventors: Robert SOUTHWORTH, Rong PAN, Tony HURSON, Siqi LIU
  • Patent number: 11489789
    Abstract: Technologies for adaptive network packet egress scheduling include a switch configured to configure an eligibility table for a plurality of ports of the switch, wherein the eligibility table includes a plurality of rounds. The switch is further configured to retrieve an eligible mask corresponding to a round of a plurality of rounds of the eligibility table presently being scheduled and determine a ready mask that indicates a ready status of each port. The switch is further configured to determine, for each port, whether the eligible status and the ready status indicate that port is both eligible and ready, and schedule, in response to a determination that at least one port has been determined to be both eligible and ready, each of the at least one port that has been determined to be both eligible and ready. Additional embodiments are described herein.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 1, 2022
    Assignee: Intel Corporation
    Inventors: Carl Geoffrion, Robert Southworth, Charles Atkin, Sanjeev Jain
  • Patent number: 11381515
    Abstract: Examples herein relate to allocation of an intermediate queue to a flow or traffic class (or other allocation) of packets prior to transmission to a network. Various types of intermediate queues are available for selection. An intermediate queue can be shallow and have an associated throughput that attempts to meet or exceed latency guarantees for a packet flow or traffic class. Another intermediate queue is larger in size and expandable and can be used for packets that are sensitive to egress port incast such as latency sensitive packets. Yet another intermediate queue is expandable but provides no guarantee on maximum end-to-end latency and can be used for packets where dropping is to be avoided. Intermediate queues can be deallocated after a flow or traffic class ends and related memory space can be used for another intermediate queue.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Arvind Srinivasan, Robert Southworth, Helia A. Naeimi
  • Publication number: 20220210075
    Abstract: Examples described herein relate to a switch, when operational, that is configured to receive in a packet an indicator of number of remaining bytes in a flow and to selectively send a congestion message based on a fullness level of a buffer and indication of remainder of the flow. In some examples, the indicator is received in an Internet Protocol version 4 consistent Options header field or Internet Protocol version 6 consistent Flow label field. In some examples, the congestion message comprises one or more of: an Explicit Congestion Control Notification (ECN), priority-based flow control (PFC), and/or in-band telemetry (INT). In some examples, to selectively send a congestion message to a transmitter based on a fullness level of a buffer that stored the packet and the number of remaining bytes in flow, the switch is to determine whether the buffer is large enough to store the remaining bytes in the flow.
    Type: Application
    Filed: October 29, 2021
    Publication date: June 30, 2022
    Inventors: Malek MUSLEH, Gene WU, Anupama KURPAD, Allister ALEMANIA, Roberto PENARANDA CEBRIAN, Robert SOUTHWORTH, Pedro YEBENES SEGURA, Curt E. BRUNS, Sujoy SEN
  • Publication number: 20220124035
    Abstract: Examples described herein relate to a switch circuitry that includes circuitry to determine if a received packet comprises a control packet; circuitry to determine congestion metrics based on receipt of at least one control packet, wherein the at least one control packet comprises a Request To Send (RTS) or Clear To Send (CTS); and circuitry to transmit at least one of the congestion metrics in at least one packet to a sender and/or receiver network interface device.
    Type: Application
    Filed: December 24, 2021
    Publication date: April 21, 2022
    Inventors: Junggun LEE, Jeremias BLENDIN, Yanfang LE, Rong PAN, Mark DEBBAGE, Robert SOUTHWORTH
  • Publication number: 20220103479
    Abstract: Examples described herein relate to a sender network interface device transmitting one or more packet probes to a receiver device, when a link is underutilized, to request information concerning link or path utilization. Based on responses to the packet probes, the sender network interface device can determine a packet transmit rate of packets of one or more flows and adjust the packet transmit rate of packets of one or more flows to increase utilization of the link.
    Type: Application
    Filed: December 8, 2021
    Publication date: March 31, 2022
    Inventors: Pedro YEBENES SEGURA, Roberto PENARANDA CEBRIAN, Rong PAN, Robert SOUTHWORTH, Allister ALEMANIA, Malek MUSLEH
  • Publication number: 20220103484
    Abstract: Examples described herein relate to a network interface device that is to adjust a transmission rate of packets based on a number of flows contributing to congestion and/or based on whether latency is increasing or decreasing. In some examples, adjusting the transmission rate of packets based on a number of flows contributing to congestion comprises adjust an additive increase (AI) parameter based on the number of flows contributing to congestion. In some examples, latency is based on a measured roundtrip time and a baseline roundtrip time.
    Type: Application
    Filed: December 8, 2021
    Publication date: March 31, 2022
    Inventors: Roberto PENARANDA CEBRIAN, Robert SOUTHWORTH, Pedro YEBENES SEGURA, Rong PAN, Allister ALEMANIA, Nayan Amrutlal SUTHAR, Malek MUSLEH
  • Publication number: 20220014478
    Abstract: Examples described herein relate to a network interface device comprising dataplane circuitry, when operational, is to generate a representation of aggregated network resource consumption information based on network resource consumption at the network interface device or at least one other network device and to transmit at least one packet with a multi-bit representation of the aggregated network resource consumption information to a second network interface device. In some examples, the network resource consumption information comprises one or more of: available transmit bandwidth, transmit bandwidth used by a queue or flow, queue depth, measured queueing time duration, expected queueing time duration, packet latency, or normalized in-flight bytes.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Inventors: Junggun LEE, Rong PAN, Robert SOUTHWORTH, Gary MUNTZ, Changhoon KIM
  • Publication number: 20210359955
    Abstract: Examples described herein relate to a network interface device comprising: a host interface, a direct memory access (DMA) engine, and circuitry to allocate a region in a cache to store a context of a connection. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on connection reliability and wherein connection reliability comprises use of a reliable transport protocol or non-use of a reliable transport protocol. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on expected length of runtime of the connection and the expected length of runtime of the connection is based on a historic average amount of time the context for the connection was stored in the cache. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on content transmitted and the content transmitted comprises congestion messaging payload or acknowledgement.
    Type: Application
    Filed: July 23, 2021
    Publication date: November 18, 2021
    Inventors: Malek MUSLEH, Tony HURSON, Pedro YEBENES SEGURA, Allister ALEMANIA, Roberto PENARANDA CEBRIAN, Ayan BANERJEE, Robert SOUTHWORTH, Sujoy SEN, Curt E. BRUNS
  • Patent number: 11108697
    Abstract: Technologies for controlling jitter at network packet egress at a source computing device include determining a switch time delta as a difference between a present switch time and a previously captured switch time upon receipt of a network packet scheduled for transmission to a target computing device and determining a host scheduler time delta as a difference between a host scheduler timestamp associated with the received network packet and a previously captured host scheduler timestamp. The source computing device is additionally configured to determine an amount of previously captured tokens present in a token bucket, determine whether there are a sufficient number of tokens available in the token bucket to transmit the received packet as a function of the switch time delta, the host scheduler time delta, and the amount of previously captured tokens present in the token bucket, and schedule the received network packet for transmission upon a determination that sufficient tokens in the token bucket.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Chih-Jen Chang, Robert Southworth, Naru Dames Sundar, Yue Yang, Charles Michael Atkin, John Leshchuk
  • Patent number: 11050554
    Abstract: Technologies for managing exact match hash table growth include a network computing device which includes a compute engine and a network interface controller (NIC). The NIC is configured to allocate a plurality of physical bucket addresses in non-contiguous chunks of memory of the compute engine, configure a bucket threshold value as a function of a hash size of the hash table, generate a plurality of virtual bucket addresses as a function of the bucket threshold value, and map each generated virtual bucket address to an allocated physical bucket address. Other embodiments are described herein.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Naru Sundar, Chih-Jen Chang, Robert Southworth, Hsi-Cheng Chu
  • Publication number: 20210119930
    Abstract: Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in the packet, and transmit the packet. In some examples, if the packet is a re-transmit of a previously transmitted packet, the circuitry is to: select a path for the re-transmit packet, and set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet.
    Type: Application
    Filed: October 29, 2020
    Publication date: April 22, 2021
    Inventors: Mark DEBBAGE, Robert SOUTHWORTH, Arvind SRINIVASAN, Cheolmin PARK, Todd RIMMER, Brian S. HAUSAUER
  • Publication number: 20210112002
    Abstract: Examples described herein relate to a network agent, when operational, to: receive a packet, determine transmit rate-related information for a sender network device based at least on operational and telemetry information accumulated in the received packet, and transmit the transmit rate-related information to the sender network device. In some examples, the network agent includes a network device coupled to a server, a server, or a network device. In some examples, the operational and telemetry information comprises: telemetry information generated by at least one network device in a path from the sender network device to the network agent.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Rong Pan, Pedro Yebenes Sugura, Roberto Penaranda Cebrian, Robert Southworth, Malek Musleh, Jeongkeun Lee, Changhoon Kim
  • Publication number: 20210092069
    Abstract: Examples described herein relate to a network interface and at least one processor that is to indicate whether data is associated with a machine learning operation or non-machine learning operation to manage traversal of the data through one or more network elements to a destination network element and cause the network interface to include an indication in a packet of whether the packet includes machine learning data or non-machine learning data. In some examples, the indication in a packet of whether the packet includes machine learning data or non-machine learning data comprises a priority level and wherein one or more higher priority levels identify machine learning data. In some examples, for machine learning data, the priority level is based on whether the data is associated with inference, training, or re-training operations. In some examples, for machine learning data, the priority level is based on whether the data is associated with real-time or time insensitive inference operations.
    Type: Application
    Filed: December 10, 2020
    Publication date: March 25, 2021
    Inventors: Malek MUSLEH, Anupama KURPAD, Roberto PENARANDA CEBRIAN, Allister ALEMANIA, Pedro YEBENES SEGURA, Curt E. BRUNS, Robert SOUTHWORTH, Sujoy SEN