Abstract: A process for fabricating a monolithic integrated circuit having matched semiconductor devices and P-N junction isolation regions, with the collector regions for the semiconductor devices of one polarity type and the isolation regions being formed by up-diffusing impurities from a selected surface of a substrate of one conductivity type though an epitaxial layer of opposite conductivity type formed thereon, so that such collector regions are surrounded by material of opposite conductivity type, and the P-N junction isolation regions selectively isolate semiconductor devices of opposite polarity type from other circuit elements, wherein such collector regions and P-N junction isolation regions have retrograded impurity concentration profiles.

Abstract: High reliability, very high slewing rates and fast settling times are realized in an operational amplifier circuit having a single externally controllable gain stage and an input stage that utilizes complementary bipolar transistors and dielectric isolation. The input stage comprises the parallel arrangement of two emitter-follower composite transistors. Each emitter-follower composite transistor consists of the parallel arrangement of two series connected NPN transistors and two series connected PNP transistors. The transistors are connected so that the base current of the PNP transistors supplies base current to the NPN transistors. Dielectric isolation is provided by means of SiO.sub.2.