Patents by Inventor Robert A. Wallis

Robert A. Wallis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12129214
    Abstract: An apparatus for producing pozzolanic material from waste includes a glass separator unit to remove glass material from the waste and a size reduction unit downstream the glass separator unit. The glass separator unit includes an outer member and a wound member positioned within the outer member and defining an open central bore. The outer member and the open central bore define respective longitudinal axes extending on a common plane that are disposed at an angle relative to a horizontal reference plane, with the inlet higher than the outlet. Non-glass/non-ceramic material is output through the open outlet end of outer member utilizing a flow of separation fluid. The glass/ceramic material is output to the size reduction unit through the open inlet end of the outer member utilizing the rotating wound member of the glass separator unit.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: October 29, 2024
    Assignee: KLAW Industries LLC
    Inventors: Jacob Robert Kumpon, Tanner Lee Wallis, Jack Paulin Lamuraglia
  • Patent number: 12119388
    Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: October 15, 2024
    Assignee: Paragraf Limited
    Inventors: Thomas James Badcock, Robert Wallis, Ivor Guiney, Simon Thomas
  • Patent number: 12084758
    Abstract: The present invention provides a method for the production of an electronic device, the method comprising: (i) providing a substrate comprising first and second layers on a heated susceptor in a reaction chamber, the chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the substrate and have a constant separation from the substrate, (ii) supplying a flow comprising a precursor compound through the inlets and into the reaction chamber to thereby decompose the precursor compound and form a graphene layer structure on a surface of the first layer of the substrate, wherein the inlets are cooled to less than 100° C. and the susceptor is heated to a temperature of at least 50° C.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: September 10, 2024
    Assignee: Paragraf Limited
    Inventors: Hugh Glass, Ivor Guiney, Martin Tyler, Robert Wallis, Rosie Baines, Simon Thomas
  • Patent number: 12080113
    Abstract: Apparatus, device, methods and system relating to a vehicular telemetry environment for monitoring vehicle components and providing indications towards the condition of the vehicle components and providing optimal indications towards replacement or maintenance of vehicle components before vehicle component failure.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: September 3, 2024
    Assignee: Geotab Inc.
    Inventors: John Robert Ford Kyes, Mark Jeffrey Davidson, Thomas Arthur Walli
  • Patent number: 12067815
    Abstract: Apparatus, device, methods and system relating to a vehicular telemetry environment for monitoring vehicle components and providing indications towards the condition of the vehicle components and providing optimal indications towards replacement or maintenance of vehicle components before vehicle component failure.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: August 20, 2024
    Assignee: Geotab Inc.
    Inventors: John Robert Ford Kyes, Mark Jeffrey Davidson, Thomas Arthur Walli
  • Patent number: 12056966
    Abstract: Apparatus, device, methods and system relating to a vehicular telemetry environment for monitoring vehicle components and providing indications towards the condition of the vehicle components and providing optimal indications towards replacement or maintenance of vehicle components before vehicle component failure.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: August 6, 2024
    Assignee: Geotab Inc.
    Inventors: John Robert Ford Kyes, Mark Jeffrey Davidson, Thomas Arthur Walli
  • Patent number: 12002870
    Abstract: There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n?1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: June 4, 2024
    Assignee: Paragraf Limited
    Inventors: Thomas James Badcock, Robert Wallis, Ivor Guiney, Simon Thomas
  • Publication number: 20240063289
    Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Applicant: PARAGRAF LIMITED
    Inventors: Thomas James Badcock, Robert Wallis, Ivor Guiney, Simon Thomas
  • Publication number: 20240047551
    Abstract: The present invention provides method for forming a diode, the method comprises providing a first graphene layer structure on a first substrate; providing a second graphene layer structure on a second substrate; treating the first graphene layer structure with an oxidant to form a graphene oxide surface thereon; and aligning the second graphene layer structure against the graphene oxide surface of the first graphene layer structure.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 8, 2024
    Applicant: PARAGRAF LIMITED
    Inventor: Robert WALLIS
  • Patent number: 11830925
    Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: November 28, 2023
    Assignee: Paragraf Limited
    Inventors: Thomas James Badcock, Robert Wallis, Ivor Guiney, Simon Thomas
  • Publication number: 20230361761
    Abstract: According to a first aspect of the disclosure, an integrated frequency multiplier circuit is provided. The circuit comprises a substrate, a strip of graphene, first and second electrode, a dielectric layer, a frequency input electrode, and a frequency output electrode. The strip of graphene has a uniform width provided on the substrate, the strip having a width x and a length y extending from a first end to a second end. The first and second electrodes are provided in electrical contact with the strip of graphene at the first and second ends of the strip of graphene respectively. The dielectric layer is provided on the strip of graphene, wherein the dielectric layer is provided across the width x of the strip of graphene. The frequency input electrode is formed on the dielectric layer, wherein the frequency input electrode is provided across the width x of the strip of graphene.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 9, 2023
    Applicant: Paragraf Limited
    Inventors: Ivor GUINEY, Thomas James BADCOCK, Robert WALLIS
  • Publication number: 20230098791
    Abstract: There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n?1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.
    Type: Application
    Filed: December 6, 2022
    Publication date: March 30, 2023
    Applicant: PARAGRAF LIMITED
    Inventors: Thomas James Badcock, Robert Wallis, Ivor Guiney, Simon Thomas
  • Patent number: 11545558
    Abstract: There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n?1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: January 3, 2023
    Assignee: Paragraf Limited
    Inventors: Thomas James Badcock, Robert Wallis, Ivor Guiney, Simon Thomas
  • Publication number: 20220290296
    Abstract: The present invention provides a method for the production of a polymer-coated graphene layer structure, the method comprising: providing a substrate on a heated susceptor in a reaction chamber, the chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the substrate and have a constant separation from the substrate, supplying a flow comprising a precursor compound through the inlets and into the reaction chamber to thereby decompose the precursor compound and form a graphene layer structure on the substrate, wherein the inlets are cooled to less than 100° C. and the susceptor is heated to a temperature of at least 50° C.
    Type: Application
    Filed: July 7, 2020
    Publication date: September 15, 2022
    Applicant: PARAGRAF LIMITED
    Inventors: Hugh GLASS, Ivor GUINEY, Martin TYLER, Robert WALLIS, Simon THOMAS
  • Publication number: 20220102525
    Abstract: There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n?1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 31, 2022
    Applicant: PARAGRAF LIMITED
    Inventors: Thomas James Badcock, Robert Wallis, Ivor Guiney, Simon Thomas
  • Publication number: 20220102526
    Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 31, 2022
    Applicant: PARAGRAF LIMITED
    Inventors: Thomas James Badcock, Robert Wallis, Ivor Guiney, Simon Thomas
  • Publication number: 20220093852
    Abstract: Methods of providing an air- and/or moisture-barrier coating on at least a portion of a two-dimensional material are described. In particular, the methods provide an improved approach for providing a doped two-dimensional material, preferably graphene, on a substrate wherein at least a portion of the two-dimensional material is coated with an air- and/or moisture-barrier coating that comprises an inorganic oxide, fluoride or sulfide. Two-dimensional materials provided with an air- and/or moisture impermeable inorganic oxide, fluoride or sulfide coating and an electronic device comprising the same are also described.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 24, 2022
    Applicant: PARAGRAF LIMITED
    Inventors: Robert Wallis, Hugh Glass, Martin Tyler, Simon Thomas, Ivor Guiney
  • Patent number: 10936649
    Abstract: An embodiment of the invention may include a method, computer program product and computer system for profile picture selection. The method, computer program product and computer system may include a computing device which may classify user photographs in user account data into one or more photograph classifications. The computing device may classify an emotion conveyed by a media interaction by the user and select a classified user photograph matching the emotion conveyed by the media interaction by the user. The computing device may display selected user photograph with the media interaction by the user.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Wallis, Richard Welp, James David Whitaker
  • Publication number: 20200134031
    Abstract: An embodiment of the invention may include a method, computer program product and computer system for profile picture selection. The method, computer program product and computer system may include a computing device which may classify user photographs in user account data into one or more photograph classifications. The computing device may classify an emotion conveyed by a media interaction by the user and select a classified user photograph matching the emotion conveyed by the media interaction by the user. The computing device may display selected user photograph with the media interaction by the user.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 30, 2020
    Inventors: Robert Wallis, Richard Welp, James David Whitaker
  • Patent number: 9476724
    Abstract: Embodiments relate to providing navigation instructions to a user for reaching a destination via a route planned on a map of a navigation system, said map comprising a plurality of road segments, at least a subset of said road segments comprising an assigned familiarity score. An aspect includes tracking a route taken by a user. Another aspect includes calculating an updated familiarity score of the one or more road segments of the tracked route using at least one of a user-defined updating variable and an updating variable based on at least one dynamically obtained actual travelling condition. Yet another aspect includes storing the updated familiarity score in a data storage of the navigation system.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: October 25, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Horatio Caine, Daniel S. Houston, Mihail S. Krastev, Robert A. Wallis