Abstract: The invention relates to a composition comprising A) a polyester, B) a polyolefin and C) a compatibilizer, wherein A) comprises a first polyester derived from an aromatic dicarboxylic acid, an acyclic aliphatic diol and at least one of a cycloaliphatic diol and spiroglycol and a second polyester different from the first polyester. The invention further relates to an article comprising the composition, particularly a toy block.

Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.

Abstract: A Doherty amplifier system is disclosed. A main amplifier is configured to receive a first portion of a radio frequency (RF) signal at a main input and provide an amplified copy of the first portion of the RF signal at a main output. A peaking amplifier is configured to be controllably activated to receive a second portion of the RF signal at a peak input and provide an amplified copy of the second portion of the RF signal at a peak output. A saturation detector has a detector input coupled to the main output of the main amplifier and a first detector control output, wherein the saturation detector is configured to detect saturation of the main amplifier and activate the peaking amplifier as saturation of the main amplifier is detected and deactivate the peaking amplifier when saturation of the main amplifier is not detected by the saturation detector.

Abstract: A power amplifier system having a power amplifier with a signal input and a signal output and bias circuitry is disclosed. The bias circuitry includes a bandgap reference circuit coupled between a reference node and a fixed voltage node. A bias generator has a bias input coupled to the reference node and a bias output coupled to the signal input. Also included is a first digital-to-analog converter having a first converter output coupled to the reference node, a first voltage input, and a first digital input, wherein the first digital-to-analog converter is configured to adjust a reference voltage at the reference node in response to a first digital setting received at the first digital input. The first digital setting correlates with an indication of temperature of the power amplifier.

Abstract: Disclosed are conjugates including a recognition element covalently bonded to or linked through a linker to a payload. The payload is a pharmaceutical agent (e.g., an antineoplastic agent, anti-infective agent, or anti-inflammatory agent) or a diagnostic agent. Also disclosed are methods of using the conjugates.

Abstract: A multi-radio access technology (RAT) circuit is provided. The multi-RAT circuit includes a radio frequency (RF) circuit(s) coupled to an interconnect medium(s). The RF circuit(s) includes a power head circuit configured to receive a local oscillation (LO) pilot and an RF signal via the interconnect medium(s). The power head circuit generates an LO signal based on the LO pilot without requiring a synthesizer. Accordingly, the power head circuit modulates the RF signal to a carrier band based on the LO signal for transmission in a millimeter wave (mmWave) spectrum. By generating the LO signal and modulating the RF signal to the carrier band in the power head circuit, it may be possible to minimize attenuation and/or interference to the RF signal. Further, it may also be possible to share the interconnect medium(s) with existing RATs, thus helping to reduce size, power, and cost impacts associated with supporting an mmWave RAT.

Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

Abstract: A novel and useful modified semiconductor fabrication technique for realizing reliable semiconductor quantum structures. Quantum structures require a minimization of the parasitic capacitance of the control gate and the quantum well. The modified semiconductor process eliminates the fabrication of the metal, contact, and optionally the raised diffusion layers from the quantum wells, thereby resulting in much lower well and gate capacitances and therefore larger Coulomb blockade voltages. This allows easier implementation of the electronic control circuits in that they can have larger intrinsic noise and relaxed analog resolution. Several processes are disclosed including implementations of semiconductor quantum structures with tunneling through an oxide layer as well as tunneling through a local well depleted region. These techniques can be used in both planar semiconductor processes and 3D, e.g., FinFET, semiconductor processes. A dedicated process masking step is used for realizing the raised diffusions.

Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.

Abstract: A multi-layer antenna assembly and related antenna array are provided. In one aspect, a multi-layer antenna assembly includes a first radiating layer(s) and a second radiating layer(s). The second radiating layer(s) is provided below and in parallel to the first radiating layer(s). The second radiating layer(s) overlaps at least partially with the first radiating layer(s). In this regard, an electromagnetic wave radiated vertically from the second radiating layer(s) is horizontally guided by an overlapping portion of the first radiating layer(s). In another aspect, an antenna array can be configured to include a number of multi-layer antenna assemblies to enable radio frequency (RF) beamforming. By employing the multi-layer antenna assemblies in the antenna array, it may be possible to flexibly and naturally steer an RF beam in a desired direction(s) without causing oversized side lobes, thus helping to improve power efficiency and performance of the antenna array.

Abstract: A radio frequency switch having an N number of switch cells coupled in series is disclosed. Each of the switch cells includes a field-effect transistor (FET), wherein a source of switch cell 1 is coupled to a first port, a drain of switch cell N is coupled to a second port, and a drain of switch cell X is coupled to a source of switch cell X+1 for switch cell 1 through switch cell N. A first diode stack has a first anode coupled to the body of switch cell X and a first cathode coupled to a drain of switch cell X+1 for switch cell 1 through switch cell N?1, and a second diode stack has a second anode coupled to the body of switch cell X and a second cathode coupled to the source of switch cell X?1 for switch cell 2 through switch cell N.

Abstract: A power amplifier apparatus supporting reverse intermodulation product (rIMD) cancellation is provided. The power amplifier apparatus includes an amplifier circuit configured to amplify and output a radio frequency (RF) signal for transmission via an antenna port. The antenna port may receive a reverse interference signal, which may interfere with the RF signal to create a rIMD(s) that can fall within an RF receive band(s). A reverse coupling circuit is provided in the power amplifier apparatus to generate an interference cancellation signal based on the reverse interference signal. The amplifier circuit is configured to amplify the interference cancellation signal and the RF signal to create an intermodulation product(s) to suppress the rIMD(s) to a determined threshold. By suppressing the rIMD(s) in the power amplifier apparatus, it is possible to support concurrent transmissions and receptions in a number of RF spectrums while in compliance with stringent regulatory spurious emissions (SEM) requirements.

Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.

Abstract: Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier.

Abstract: RF communications circuitry, which includes a first tunable RF filter and a first RF low noise amplifier (LNA) is disclosed. The first tunable RF filter includes a pair of weakly coupled resonators, and receives and filters a first upstream RF signal to provide a first filtered RF signal. The first RF LNA is coupled to the first tunable RF filter, and receives and amplifies an RF input signal to provide an RF output signal.

Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

Abstract: Power amplifier (PA) output memory neutralization is disclosed, using baseband input/output (I/O) capacitance current compensation. Radio frequency (RF) PAs experience I/O memory effects when used with envelope tracking supply modulation schemes. Envelope tracking supply modulation results in a nonlinear variation of the I/O capacitance. Traditional approaches compensate for such effects with a current provided by a bias circuit which is band-limited. This results in memory effects which distort the amplified signal, becoming more significant as the modulation bandwidth increases. An RF communications system according to embodiments disclosed herein mitigates such memory effects by compensating for the non-linear effect of the I/O capacitance in an RF PA.

Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.

Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.

Abstract: A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core.